公开(公告)号：EP1955167A2

公开(公告)日：2008-08-13

申请号：EP06849059.8

申请日：2006-11-27

Applicant: Novelics LLC

Inventor： WINOGRAD, Gil, I. ,  AFGHAHI, Morteza ,  TERZIOGLU, Esin

IPC: G06F12/00

CPC classification number: G11C17/10 ,  H01L27/112 ,  H01L27/11226

Abstract: In one embodiment, a read-only memory (ROM) is provided that includes: a plurality of word lines; a plurality of bit lines; a plurality of memory cell transistors arranged in rows corresponding to the word lines such that if a word line is asserted the corresponding memory cell transistors are conducting, the memory cell transistors also being arranged in columns corresponding to the bit lines; wherein each column of memory cell transistors is arranged into column groups, each column group including an access transistor coupled to the corresponding bit line, the remaining transistors in the column group being coupled in series from the access transistor to a last transistor in the column group, the last transistor in the column group being coupled to a voltage node.

公开(公告)号：EP1925084A2

公开(公告)日：2008-05-28

申请号：EP06789891.6

申请日：2006-08-16

Applicant: Novelics

Inventor： AFGHAHI, Morteza ,  TERZIOGLU, Esin ,  WINOGRAD, Gil, I.

IPC: H03K19/003

CPC classification number: H03K19/0016

Abstract: In one embodiment, NMOS transistors have their source coupled to a common source node such that the NMOS transistors conduct a leakage current if the common source node is grounded. To reduce this leakage current, the common source node is raised in potential. Similarly, PMOS transistors have their source coupled to a common source node such that the PMOS transistors conduct a leakage current if the common source node is charged to a power supply voltage VDD. To reduce this leakage current, the common source node is lowered in potential.

Abstract translation: 在一个实施例中，NMOS晶体管的源极耦合到公共源极节点，使得如果公共源极节点接地，NMOS晶体管传导漏电流。 为了减少这种泄漏电流，公共源极节点的电位升高。 类似地，PMOS晶体管的源极耦合到公共源极节点，使得如果公共源极节点被充电到电源电压VDD，则PMOS晶体管传导泄漏电流。 为了减少这种泄漏电流，公共源节点的电位降低。

公开(公告)号：EP1934982A2

公开(公告)日：2008-06-25

申请号：EP06801760.7

申请日：2006-08-16

Applicant: Novelics

Inventor： TERZIOGLU, Esin ,  WINOGRAD, Gil, I. ,  AFGHAHI, Morteza, Cyrus

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.