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公开(公告)号：EP2704012A8
公开(公告)日：2014-04-30
申请号：EP13179559.3
申请日：2013-08-07
Applicant: Freescale Semiconductor, Inc.
Inventor： Cunningham, Jeffrey C. , Gasquet, Horatio P. , Scouller, Ross S. , Cabassi, Marco A.
CPC classification number: G06F11/1048 , G11C29/026 , G11C29/028
Abstract: Methods and systems are disclosed for adaptive error correction for non-volatile memories that dynamically adjust sense amplifier read detection windows. Memory control circuitry (120) uses error correction code (ECC) routines (124) to detect bit errors that are non-correctable using these ECC routines. The memory control circuitry (120) then dynamically adjusts sense amplifier read detection windows (312) to allow for correct data to be determined. Corrected data can then be output to external circuitry. The corrected data can also be stored for later access when subsequent read operations attempt to access address locations that previously suffered bit failures. The disclosed methods and systems can also be used with respect to memories that are not non-volatile memories.
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公开(公告)号：EP1770708B1
公开(公告)日：2012-11-14
申请号：EP06125238.3
申请日：1999-09-20
Applicant: Freescale Semiconductor, Inc.
Inventor： Chang, Ray , Weier, William , Wong, Richard
CPC classification number: G11C7/222 , G11C7/06 , G11C7/22 , G11C29/023 , G11C29/026 , G11C29/028 , H03K5/131 , H03K5/133
Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.
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公开(公告)号：EP2003652B1
公开(公告)日：2010-11-17
申请号：EP06730214.1
申请日：2006-03-28
Applicant: Fujitsu Semiconductor Limited
Inventor： KOBAYASHI, Hiroyuki
CPC classification number: G11C29/44 , G11C11/401 , G11C29/026 , G11C29/1201 , G11C29/50 , G11C29/78
Abstract: A cell array comprises a word line and a bit line which are connected to a memory cell, and a redundant word line and a redundant bit line which are connected to a redundant memory cell. A reading section reads data held in the memory cell. A defect detecting input section receives a defect detecting signal from a test device. A dummy defect output section outputs a dummy defect signal during a predetermined period of time after the defect detecting input section receives the defect detecting signal. A data output section inverts the logic of the read data outputted from a reading circuit while the dummy defect signal is activated. This enables generation of a pseudo defect by means of a semiconductor memory without changing any test device or test program. More specifically, a single bit defect can be replaced by a predetermined bit line defect or word line defect without changing any testing environment. As a result, the efficiency of the remedy can be improved to reduce the cost of the test.
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公开(公告)号：EP1934982A2
公开(公告)日：2008-06-25
申请号：EP06801760.7
申请日：2006-08-16
Applicant: Novelics
Inventor： TERZIOGLU, Esin , WINOGRAD, Gil, I. , AFGHAHI, Morteza, Cyrus
IPC: G11C7/02
CPC classification number: G11C11/4091 , G11C7/02 , G11C7/065 , G11C7/12 , G11C11/401 , G11C11/4094 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2207/2254 , H01L27/0207 , H01L27/10873 , H03K3/356034
Abstract: In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplification of the voltage difference between the pair of bit lines.
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公开(公告)号：EP1770708A2
公开(公告)日：2007-04-04
申请号：EP06125238.3
申请日：1999-09-20
Applicant: Freescale Semiconductor, Inc.
Inventor： Chang, Ray , Weier, William , Wong, Richard
CPC classification number: G11C7/222 , G11C7/06 , G11C7/22 , G11C29/023 , G11C29/026 , G11C29/028 , H03K5/131 , H03K5/133
Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.
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Patent Agency Ranking6.发明公开
公开(公告)号：EP1670001A2
公开(公告)日：2006-06-14
申请号：EP05111880.0
申请日：2005-12-09
Applicant: Saifun Semiconductors Ltd.
Inventor： Maayan, Eduardo , Cohen, Guy , Eitan, Boaz
CPC classification number: G11C29/28 , G11C16/04 , G11C16/0475 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/50 , G11C29/50004
Abstract: A method includes changing a read reference level for reading a group of memory cells as a function of changes in a threshold voltage distribution of a different group of memory cells. The changing step includes determining a history read reference level for correct reading of at least one history cell (64), selecting a memory read reference level according to the first read reference level, and reading non-volatile memory array cells (62) associated with the at least one history cell (64) using the memory read reference level.
Abstract translation: 一种方法包括根据不同组的存储器单元的阈值电压分布的变化来改变用于读取一组存储器单元的读取参考电平。 改变步骤包括确定用于正确读取至少一个历史单元（64）的历史读取参考水平，根据第一读取参考水平选择存储器读取参考水平，以及读取与...相关联的非易失性存储器阵列单元（62） 所述至少一个历史单元（64）使用所述存储器读取参考电平。
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7.发明授权
公开(公告)号：EP0929901B1
公开(公告)日：2001-11-28
申请号：EP97945392.5
申请日：1997-09-29
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： WENDELL, Dennis, L.
CPC classification number: G11C29/026 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/14 , G11C11/401 , G11C11/4087 , G11C11/41 , G11C11/412 , G11C11/418 , G11C16/04 , G11C17/14 , G11C29/02 , G11C29/021 , G11C29/025 , G11C29/028 , G11C29/18 , G11C29/32 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C29/50016 , G11C2029/5004 , G11C2029/5006 , H03K3/356156 , H03K5/13 , H03K2005/00019 , H03K2005/00071 , H03L7/08 , H03L7/0995
Abstract: A memory array test and characterization capability is disclosed which allows DC characterization of the memory cells, the bit lines, and the sense amplifiers. A row decoder is provided which includes a static wordline select signal to disable self-resetting logic within the row decoder and allow the word line to remain active for a user-controlled length of time. An analog wordline drive capability allows the active wordline to be driven to a user-controllable analog level. Direct access to a pair of bitlines is provided by a multiplexer which is statically decoded to couple a pair of isolated terminals to the respective bitlines within the decoded column. This allows DC voltage levels to be impressed upon each of the two bitlines within the decoded column and/or the two bitline currents to be sensed. A separate power connection is provided for the memory array which allows operating the memory array at a different power supply voltage than the remainder of the circuit. By utilizing one or more of these features together, several tests of the memory array may be performed, including characterizing the DC transfer function of the memory cells, the standby power of the memory array, the static noise margin of the memory cells, the alpha particle susceptibility of the memory cells as a function of memory cell supply voltage, the offset voltage of bitline sense amplifiers, and others.
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公开(公告)号：EP1033721A2
公开(公告)日：2000-09-06
申请号：EP99118540.6
申请日：1999-09-20
Applicant: MOTOROLA INC.
Inventor： Chang, Ray , Weier, William R. , Wong, Richard Y.
CPC classification number: G11C7/222 , G11C7/06 , G11C7/22 , G11C29/023 , G11C29/026 , G11C29/028 , H03K5/131 , H03K5/133
Abstract: A memory has sense amplifiers that provide data onto a global data lines that are received by secondary amplifiers. The sense amplifiers and the secondary amplifiers are enabled by clocks that are timed by programmable delay circuits. The programmable delays are programmed by delay selection circuits that provide a continuous output to the programmable delay circuits. There are two delay selection circuits. One is shared by all of the programmable delay circuits that enable the sense amplifiers, and one is shared by all of the programmable delay circuits that enable the secondary amplifiers. The outputs of these two delay selection circuits are chosen to provide the output which programs the programmable delay circuits for optimizing the worst case of the access time of the memory.
Abstract translation: 存储器具有读出放大器，将数据提供给由次级放大器接收的全局数据线。 读出放大器和次级放大器通过可编程延迟电路定时的时钟使能。 可编程延迟由延迟选择电路编程，延迟选择电路向可编程延迟电路提供连续输出。 有两个延迟选择电路。 其中一个由启用读出放大器的所有可编程延迟电路共享，而另一个由启用次级放大器的所有可编程延迟电路共享。 选择这两个延迟选择电路的输出以提供编程可编程延迟电路的输出，用于优化存储器访问时间的最坏情况。
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公开(公告)号：EP0856188B1
公开(公告)日：1999-10-27
申请号：EP96929800.9
申请日：1996-08-30
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： TANG, Yuan
CPC classification number: G11C16/3477 , G11C16/04 , G11C16/28 , G11C16/3468 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C2029/5006
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10.发明公开MEMORY SYSTEM HAVING NON-VOLATILE DATA STORAGE STRUCTURE FOR MEMORY CONTROL PARAMETERS AND METHOD 失效具有非易失性存储器结构存储系统内存控制参数和及其方法
公开(公告)号：EP0842515A4
公开(公告)日：1999-09-01
申请号：EP96926703
申请日：1996-07-09
Applicant: MICRON QUANTUM DEVICES INC
Inventor： ROOHPARVAR FRANKIE F
CPC classification number: G11C29/46 , G06F11/006 , G11C16/20 , G11C16/28 , G11C16/30 , G11C29/026 , G11C29/44
Abstract: A memory system (10) capable of being configured for optimum operation after fabrication and method of controlling the same. The system includes an array of memory cells arranged in a multiplicity of rows and a multiplicity of columns, with each cell located in one of the rows being coupled to a common word line and with each cell located in one of the columns being coupled to a common bit line. Control circuitry (19) is included for controlling memory operations, with the memory operations (16) including programming the memory cells, reading the memory cells and preferably programming the cells. A plurality of non-volatile data storage units (12A) are provided for storing control parameter data used by the controlling means for controlling the memory operations. Such control parameters may include, for example, parameters for adjusting the magnitude and duration of voltage pulses applied to the memory (10) for carrying out programming and erasing operations.
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