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公开(公告)号：EP0603942B1
公开(公告)日：1998-09-02
申请号：EP93203507.4
申请日：1993-12-14
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F1/56
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公开(公告)号：EP0346986A2
公开(公告)日：1989-12-20
申请号：EP89201505.8
申请日：1989-06-12
CPC分类号： H03D3/007 , H03D1/2245 , H03D3/006 , H03D7/165 , H03D2200/005
摘要： A zero IF receiver which is capable of detecting short duration or CW signals and of operating over a large dynamic range.
An embodiment of the receiver comprises an input terminal (10) for receiving an input signal, means (12, 18 to 26) coupled to the input for producing quadrature related, frequency down-converted first and second signals (I,Q). These first and second signals are applied to first and second amplifiers (28, 30) having a substantially sinh⁻¹ transfer characteristics to produce substantially logarithmic output signals. First and second digitising means (32, 34) are coupled to the outputs of the first and second amplifiers (28, 30), respectively; outputs of the first and second digitising means being connected to demodulating means (36). The demodulating means (36) being constructed and operated to convert the digitised in-phase andquadrature phase signals into amplitude and frequency descriptions of the input signal relative to a centre frequency of the receiver.摘要翻译： 一个能够检测短持续时间或CW信号并在大动态范围内工作的零IF接收机。 接收机的实施例包括用于接收输入信号的输入端子（10），耦合到输入的装置（12,18至26），用于产生正交相关的降频转换的第一和第二信号（I，Q）。 这些第一和第二信号被施加到具有基本上sinh <1>传输特性的第一和第二放大器（28,30），以产生基本上对数的输出信号。 第一和第二数字化装置（32,34）分别耦合到第一和第二放大器（28,30）的输出; 第一和第二数字化装置的输出连接到解调装置（36）。 解调装置（36）被构造和操作以将数字化的同相和相位相位信号转换成相对于接收机的中心频率的输入信号的幅度和频率描述。
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3.发明授权
公开(公告)号：EP0623993B1
公开(公告)日：1997-11-19
申请号：EP94200921.8
申请日：1994-04-05
CPC分类号： H03D3/007 , H03D7/1408 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0019 , H03D2200/0033
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公开(公告)号：EP0346986A3
公开(公告)日：1992-04-22
申请号：EP89201505.8
申请日：1989-06-12
CPC分类号： H03D3/007 , H03D1/2245 , H03D3/006 , H03D7/165 , H03D2200/005
摘要： A zero IF receiver which is capable of detecting short duration or CW signals and of operating over a large dynamic range. An embodiment of the receiver comprises an input terminal (10) for receiving an input signal, means (12, 18 to 26) coupled to the input for producing quadrature related, frequency down-converted first and second signals (I,Q). These first and second signals are applied to first and second amplifiers (28, 30) having a substantially sinh⁻¹ transfer characteristics to produce substantially logarithmic output signals. First and second digitising means (32, 34) are coupled to the outputs of the first and second amplifiers (28, 30), respectively; outputs of the first and second digitising means being connected to demodulating means (36). The demodulating means (36) being constructed and operated to convert the digitised in-phase andquadrature phase signals into amplitude and frequency descriptions of the input signal relative to a centre frequency of the receiver.
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5.发明公开
公开(公告)号：EP0623993A3
公开(公告)日：1995-01-18
申请号：EP94200921.8
申请日：1994-04-05
CPC分类号： H03D3/007 , H03D7/1408 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0019 , H03D2200/0033
摘要： A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages comprises a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each said Darlington circuit comprises first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current to voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.
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6.发明公开Four quadrant multiplier circuit and a receiver including such a circuit 失效Vierquadranten-Multiplizierschaltung und eine solche Schaltung enthaltenderEmpfänger。
公开(公告)号：EP0623993A2
公开(公告)日：1994-11-09
申请号：EP94200921.8
申请日：1994-04-05
CPC分类号： H03D3/007 , H03D7/1408 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0019 , H03D2200/0033
摘要： A four quadrant multiplier circuit having a high dynamic range and capable of operating at low voltages comprises a dual transconductance amplifier circuit (TAC) consisting of NPN transistors (20 to 23 and 64 to 67), coupled to a first input port (36), first and second folded Darlington circuits (57,58), and a resistive element (78). Each said Darlington circuit comprises first and second NPN transistors (68,70 and 69,71) whose emitter-collector paths are connected in series and a third PNP transistor (72,73) having its emitter-collector path connected between the collector of the first transistor (68,69) and the base electrode of the second transistor (70,71). The emitter-collector junction (76,77) of the first and second transistors (68,70 and 69,71) is connected to the base electrode of the third transistor (72,73). The resistive element (78) is connected between the base electrodes of the third transistors (72,73). A second input port (56) is connected to the base electrodes of the first transistors (68,69). The emitter currents of the dual transconductance amplifier are supplied by way of current mirror circuits (80,81) from the emitter currents of the second transistors (70,71). The transconductance amplifier circuit (TAC) may be of any suitable type which has its transconductance linearly proportional to its emitter currents. In a refinement of the circuit, the current to voltage converter function of the current mirrors is carried out by the second transistors (70,71) and the transistors (82,83) of the current mirror circuits (80,81) are omitted.
摘要翻译： 具有高动态范围且能够在低电压下操作的四象限乘法器电路包括由NPN晶体管（20至23和64至67）组成的双跨导放大器电路（TAC），耦合到第一输入端口（36）， 第一和第二折叠达林顿电路（57,58）和电阻元件（78）。 每个所述达林顿电路包括其发射极 - 集电极路径串联连接的第一和第二NPN晶体管（68,70和69,71）和第三PNP晶体管（72,73），其发射极 - 集电极路径连接在 第一晶体管（68,69）和第二晶体管（70,71）的基极。 第一和第二晶体管（68,70和69,71）的发射极 - 集电极结（76,77）连接到第三晶体管（72,73）的基极。 电阻元件（78）连接在第三晶体管（72,73）的基极之间。 第二输入端口（56）连接到第一晶体管（68,69）的基极。 双重跨导放大器的发射极电流通过来自第二晶体管（70,71）的发射极电流的电流镜电路（80,81）提供。 跨导放大器电路（TAC）可以是任何合适的类型，其跨导与其发射极电流成线性比例。 在电路的改进中，电流镜的电流到电压转换器的功能由第二晶体管（70,71）进行，并且省略电流镜电路（80,81）的晶体管（82,83）。
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公开(公告)号：EP0603942A1
公开(公告)日：1994-06-29
申请号：EP93203507.4
申请日：1993-12-14
IPC分类号： H03F3/45
CPC分类号： H03F1/3211 , H03F1/56
摘要： A transconductance amplifier comprises first and second input transistors (TO1,TO2) to the base electrodes of which an input voltage (Vi) is applied. A constant current source (10) is connected to the emitters of the input transistors. Outputs are derived from their collector electrodes. A tapped impedance having two or more segments (RO to RN,RN to RO) is connected between the base electrodes of the input transistors (TO1,TO2). The base of a further transistor (T1 to TN,TN to T1) is connected to a respective tap (a1 to aN,aN to a1) of the tapped impedance. The emitter areas (e1 to eN,eN to e1) of these further transistors increase from each end of the tapped impedance towards the centre (28) of the tapped impedance. The emitters of the further transistors (T1 to TN,TN to T1) are connected to the current source (10) and the collectors are connected to a junction (26) which is connected to means (30) for computing the combined base currents of the further transistors (T1 to TN, TN to T1) from the combined collector currents at said junction (26). The computed current is supplied by a current mirror circuit (32) to the centre (28) of the tapped impedance to pull up the voltage at the centre (28). The tapped impedance can have an increased resistance without unduly loading a preceding stage.
摘要翻译： 跨导放大器包括施加输入电压（Vi）的基极的第一和第二输入晶体管（TO1，TO2）。 恒流源（10）连接到输入晶体管的发射极。 输出源自其集电极。 具有两个或多个段（RO至RN，RN至RO）的抽头阻抗连接在输入晶体管（TO1，TO2）的基极之间。 另外的晶体管（T1至TN，TN至T1）的基极连接到抽头阻抗的各个抽头（a1至aN，aN至a1）。 这些另外的晶体管的发射极区域（e1至eN，eN至e1）从抽头阻抗的每端向抽头阻抗的中心（28）增加。 另外的晶体管（T1至TN，TN至T1）的发射极连接到电流源（10），并且集电极连接到连接到装置（30）的结（26），用于计算组合的基极电流 来自所述结（26）处的组合集电极电流的另外的晶体管（T1至TN，TN至T1）。 计算出的电流由电流镜电路（32）提供给抽头阻抗的中心（28），以将中心电压（28）拉高。 抽头阻抗可以具有增加的电阻，而不会过度地加载前一级。
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