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    TIME SERIES FORECASTING OF APPLICATION MONITORING DATA AND OBSERVABILITY DATA BY QUANTILE REGRESSION
    1.
    发明公开
    TIME SERIES FORECASTING OF APPLICATION MONITORING DATA AND OBSERVABILITY DATA BY QUANTILE REGRESSION 审中-公开

    公开(公告)号：EP4425335A2

    公开(公告)日：2024-09-04

    申请号：EP24157128.0

    申请日：2024-02-12

    Applicant: Dynatrace LLC

    Inventor： Natschlaeger, Thomas ,  Zuschrader, Magdalena ,  Kepplinger, Bernhard

    IPC: G06F11/07 ,  G06F11/34 ,  G06N7/01

    CPC classification number: G06F11/3452 ,  G06N7/01 ,  G06F2201/8120130101 ,  G06F11/0751

    Abstract: The disclosure concerns the detection of anomalies and the forecasting of application monitoring data in a distributed computing environment. The methods work well for highly correlated input data containing noise and outliers. In case of detecting an anomaly in application monitoring data, the objectives are solved by training at least two probabilistic models forecasting lower and higher quantile values based on training time series data, by receiving and extracting an actual time series, by calculating lower and a higher quantile forecasts based on the probabilistic models and the time series, by calculating a low threshold and a high threshold based on the lower and a higher quantile forecasts, and by receiving and comparing a new value to the low and high thresholds. If the new value is either smaller than the low threshold or higher than the high threshold, the new value is marked as an anomaly.

    METHOD AND APPARATUS FOR SELECTIVE INPUT/OUTPUT (IO) TERMINAL SAFE-STATING FOR INDEPENDENT ON-CHIP APPLICATIONS
    5.
    发明公开
    METHOD AND APPARATUS FOR SELECTIVE INPUT/OUTPUT (IO) TERMINAL SAFE-STATING FOR INDEPENDENT ON-CHIP APPLICATIONS 审中-公开

    公开(公告)号：EP4365741A1

    公开(公告)日：2024-05-08

    申请号：EP23205620.0

    申请日：2023-10-24

    Applicant: NXP B.V.

    Inventor： Sethi, Ankush ,  Kaul, Rohit Kumar ,  Jain, Aarul

    IPC: G06F11/07

    CPC classification number: G06F11/0793 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0751

    Abstract: A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.

    INFORMATION PROCESSING APPARATUS AND RECORDING MEDIUM STORING INFORMATION PROCESSING PROGRAM
    7.
    发明公开
    INFORMATION PROCESSING APPARATUS AND RECORDING MEDIUM STORING INFORMATION PROCESSING PROGRAM 审中-公开

    公开(公告)号：EP3407552A1

    公开(公告)日：2018-11-28

    申请号：EP18174007.7

    申请日：2018-05-24

    Applicant: FUJITSU LIMITED

    Inventor： Fujimori, Takafumi ,  Kobayashi, Shimuya

    IPC: H04L12/707 ,  H04L12/703

    CPC classification number: G06F13/4022 ,  G06F11/0745 ,  G06F11/0751 ,  G06F11/0772 ,  H04L45/22 ,  H04L45/28

    Abstract: An information processing apparatus includes: a first apparatus including: a first hardware, a first controller that manages the first hardware, and a first switch that switches connection between the first hardware, the first controller, and a second apparatus; and the second apparatus including: a second hardware, a second controller that manages the second hardware, and a second switch that switches connection between the second hardware, the second controller, and the first apparatus, wherein the first switch performs control to couple the first controller to a first signal line between the first apparatus and the second apparatus, the second switch performs control to couple the second hardware to the first signal line, and the first controller obtains information output from the second hardware through the first signal line coupled to the second hardware.

    ANOMALY DETECTION IN TIME SERIES
    9.
    发明公开
    ANOMALY DETECTION IN TIME SERIES 审中-公开

    公开(公告)号：EP3401789A1

    公开(公告)日：2018-11-14

    申请号：EP17170071.9

    申请日：2017-05-09

    Applicant: Skyline Communications NV

    Inventor： Lapon, Jorn ,  Ledoux, Veerle ,  Dreesen, Dennis ,  Ferranti, Micol

    IPC: G06F11/07

    CPC classification number: G06F11/0751

    Abstract: A method for detection of anomalies in a time series is disclosed comprising: a) obtaining (301) a next value of the time series; b) updating (303, 323) a plurality of derived time series thereby obtaining a next derived value; c) predicting (304, 324), a future derived value (320, 321) of the derived time series and a confidence indicator; d) retrieving, a previously predicted derived value (322, 323) and a confidence indicator of the previously predicted derived value as a prediction of the next derived value; e) detecting (306, 326) a change point when the difference between the next derived value and the previously predicted derived value is larger than indicated by the confidence indicator of the previously predicted derived value; f) detecting (307) an anomaly in the time series based on the detection (306, 326) of one or more change points at the one or more resolutions of the derived time series.

    INPUT CONGRUENCE SYSTEM FOR FLIGHT CONTROL SURFACES
    10.
    发明授权
    INPUT CONGRUENCE SYSTEM FOR FLIGHT CONTROL SURFACES 有权

    公开(公告)号：EP2974956B1

    公开(公告)日：2018-10-17

    申请号：EP15176606.0

    申请日：2015-07-14

    Applicant: The Boeing Company

    Inventor： YEH, Ying Chin

    IPC: G06F11/07 ,  B64C13/50

    CPC classification number: B64C13/503 ,  G05D1/0055 ,  G06F11/0739 ,  G06F11/0751 ,  G06F11/079 ,  Y02T50/44

    Abstract: A method and apparatus for controlling flight control surfaces on an aircraft. Commands are sent onto a data bus system (208) from flight control modules (212). The flight control modules (212) and actuator control modules (210) determine whether an error is present in the commands sent onto the data bus system (208). Point-to-point connections between the flight control modules (214) and the actuator control modules (210) are managed based on whether the error is present in the commands sent onto the data bus system (208).

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