摘要:
An integrated memory comprising a sense amplifier which includes a parallel connection of a first and a second current branch, each current branch including channels of a control transistor and a load transistor which are coupled via a relevant junction point, the relevant junction points on the one side and gates of the load transistors on the other side being cross-wise coupled, said junction points constituting outputs of the sense amplifier, said transistors being of the same conductivity type, each load transistor being connected in a source-follower configuration with the relevant control transistor. As a result, the control transistors will be operative in the saturation region at all times and can be driven to full output, so that an integrated memory in accordance with the invention is faster.
摘要:
An integrated circuit comprises a converter for converting a logic input signal of a first logic type into a logic output signal of a second logic type, for example from ECL to CMOS level. The converter comprises a buffer (10), including a controllable load (14) and a driver transistor (12), and a control circuit (20). In dependence on a control voltage and a reference voltage (V REF ) externally applied, the load (14) is controlled so that the output signal (V OUT ) is substantially equal to the reference voltage (V REF ) if the input signal (V IN ) is substantially equal to the control voltage. The load (14) and the driver transistor (12) in the buffer are controllable in a mutually opposed manner, a capacitance (25) being inserted between the control terminal of the load and the input terminal (16) of the driver so as to pass the AC effect of signal transitions to the load, thus speeding up the transition at the buffer. In one embodiment the control circuit (20) comprises a copy (30) of the buffer (10), which copy (30) receives the control voltage on its input, its load being controlled by a differential amplifier (40) whose inputs receive the reference voltage (V REF ) and the output voltage of the copy. A CMOS-SRAM comprising ECL/CMOS level converters of the above kind communicates with fast ECL circuits and has a low energy consumption.
摘要:
A linear-gain amplifier arrangement comprises a current amplifying cell constructed by means of field-effect transistors and comprising a first (M1, M3) and a second (M2, M4) current-mirror circuit whose respective input transistors (M1; M2) and output transistors (M3; M4) constitute a first and a second differential pair. The input transistors (M1; M2) have their drain electrodes connected to a voltage-current converter (V/I) comprising field-effect transistors, which supplies difference currents (I in1 , I in2 ) which are square-law functions of the input voltage (U in ) to be amplified. The difference between these input currents (I in1 ; I in2 ) is a linear function of the input voltage (U in ). When the transistors are operated in their saturation regions the difference between the output currents (I out1 ; I out2 ) is also a linear function of the input voltage (U in ). By adding a direct voltage (V c ) to the gate-source voltage of the input and output transistors (M1, M2; M3, M4) or by adding a direct current (I c ) to the respective input currents (I in1 ; I in2 ) the gain can be varied without a change in bandwidth. When the arrangement is constructed as an integrated semiconductor circuit its gain can be made immune to temperature variations and tolerances in the fabrication process.
摘要:
The invention relates to a current amplifier comprising an input terminal (1) for receiving an input current, an output terminal (2) for supplying an output current, a first transistor (T₁) having a base-emitter junction coupled to the input terminal, and a second transistor (T₂) having a collector coupled to the output terminal and having an emitter arranged in series with a voltage source (4), the series arrangement of the voltage source and the base-emitter junction of the second transistor being arranged in parallel with the base-emitter junction of the first transistor, the first transistor being of the NPN conductivity type and the second transistor being of the PNP conductivity type. The low internal series resistor of the NPN transistor T₁ allows a comparatively large input current I in , so that the attenuated output current (I out ) is a linear function of the input current over a wide range. This results in a current-sourcing attenuating current mirror having a far better linearity than a current amplifier in which the first and the second transistor are both of the PNP conductivity type.
摘要:
A first and a second transistor (T,, T 2 ) whose emitters are connected to a common point (4) via first resistors (R 1 , R 2 ), which common point is connected to the positive power-supply terminal via a current source (I 1 ), form a differential amplifier to which an input signal (V i ) is applied. In order to increase the slew rate the quiescent current through the first and the second transistor (T 1 , T 2 ) is made to increase when the input voltage (V i ) increases. This is achieved by means of a third transistor (T 3 ) whose emitter is connected to the common point (4). The base of this transistor (T 3 ) is connected to the tapping of a voltage divider which is arranged between the bases of the first and the second transistor (T 1 , T 2 ) and which comprises second resistors (R 3 , R 4 ). When the input voltage increases the transistor (T 3 ) drains a continually decreasing portion of the current from the current source (I 1 ).