公开(公告)号：EP4348872A1

公开(公告)日：2024-04-10

申请号：EP22723908.4

申请日：2022-04-27

申请人： QUALCOMM INCORPORATED

发明人： JIAN, Yung-Yih ,  HSU, Chun-Hao ,  ANG, Peter Pui Lok ,  GOROKHOV, Alexei Yurievitch ,  CHEN, Andrew ,  LIU, Ping ,  SAIKRISHNA VASUDEVAN, Fnu ,  SWAMI, Arundhathi Rajshekher ,  CHANDRA, Madhup ,  MAHESHWARI, Shailesh

IPC分类号： H04B7/08 ,  H04B7/0413 ,  H04W72/12

公开(公告)号：EP3257080A1

公开(公告)日：2017-12-20

申请号：EP15805719.0

申请日：2015-11-25

申请人： QUALCOMM Incorporated

发明人： MOJUMDER, Niladri Narayan ,  CHABA, Ritu ,  LIU, Ping ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： H01L27/02 ,  G11C8/14 ,  G11C11/418 ,  H01L27/11

CPC分类号： H01L27/1104 ,  G11C8/14 ,  G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  H01L21/3213 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11

摘要： An apparatus includes a first metal layer coupled to a bit cell. The apparatus also includes a third metal layer including a write word line that is coupled to the bit cell. The apparatus further includes a second metal layer between the first metal layer and the third metal layer. The second metal layer includes two read word lines coupled to the bit cell.

公开(公告)号：EP3271921A1

公开(公告)日：2018-01-24

申请号：EP16711416.4

申请日：2016-03-01

申请人： Qualcomm Incorporated

发明人： MOJUMDER, Niladri, Narayan ,  LIU, Ping ,  SONG, Stanley, Seungchul ,  WANG, Zhongze ,  YEAP, Choh, Fei

IPC分类号： G11C11/413 ,  G11C11/417 ,  G11C11/419 ,  G11C29/02 ,  G11C29/54

CPC分类号： G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

摘要： Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.