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    METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE
    1.
    发明公开
    METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE 审中-公开
    方法和设备，用于测试存储部件

    公开(公告)号：EP2208203A2

    公开(公告)日：2010-07-21

    申请号：EP07844691.1

    申请日：2007-10-29

    申请人： Agere Systems, Inc.

    发明人： KOHLER, Ross, A. ,  MCPARTLAND, Richard, J. ,  WERNER, Wayne, E.

    IPC分类号： G11C29/50

    CPC分类号： G11C8/08 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1202

    摘要： Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters.

    Semiconductor memory device
    2.
    发明公开
    Semiconductor memory device 审中-公开
    Halbleiter-Speicherbauteil

    公开(公告)号：EP1280205A2

    公开(公告)日：2003-01-29

    申请号：EP01123208.9

    申请日：2001-10-01

    申请人： Kabushiki Kaisha Toshiba

    发明人： Ohsawa, Takashi

    IPC分类号： H01L27/108

    CPC分类号： H01L29/7841 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/1202 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1082 ,  H01L27/10823 ,  H01L27/10897 ,  H01L27/1203

    摘要： A semiconductor memory device has full depletion type MISFETS to constitute memory cells (MC) on a semiconductor substrate (11) via an insulating film (12). Each MISFET has a semiconductor layer (13), a source region (16), a drain region (17), the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (15) on a first side of the channel body, and an auxiliary gate (18) on a second side of the channel body. With a state, in which the channel body is fully depleted by an electric field from the main gate and a portion of the second side of the channel body is capable of accumulating majority carriers by an electric field from the auxiliary gate, as a reference state, the MISFET has a first data state in which the majority carriers are accumulated and a second data state in which the majority carriers are emitted.

    摘要翻译： 半导体存储器件具有通过绝缘膜（12）在半导体衬底（11）上构成存储单元（MC）的完全耗尽型MISFET。 每个MISFET具有半导体层（13），源极区（16），漏极区（17），用作浮动状态的沟道体的源极区和漏极区之间的半导体层，主栅极 ）和在通道主体的第二侧上的辅助门（18）。 利用状态，其中通道体被来自主栅极的电场完全耗尽，并且通道体的第二侧的一部分能够通过来自辅助栅极的电场累积多数载流子作为参考状态 MISFET具有多数载波被累积的第一数据状态和多数载波被发射的第二数据状态。

    DETECTION OF BROKEN WORD-LINES IN MEMORY ARRAYS
    5.
    发明公开
    DETECTION OF BROKEN WORD-LINES IN MEMORY ARRAYS 有权
    检测半导体存储器阵列断字线

    公开(公告)号：EP2591472A1

    公开(公告)日：2013-05-15

    申请号：EP11729863.8

    申请日：2011-06-24

    申请人： SanDisk Technologies Inc.

    发明人： SHAH, Grishma Shailesh ,  LI, Yan

    IPC分类号： G11C29/02

    CPC分类号： G11C29/02 ,  G11C29/025 ,  G11C29/702 ,  G11C2029/1202

    摘要： Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. In an exemplary embodiment, a program operation of the memory circuit is performed on a first plurality of memory cells along a word-line, where the programming operation includes a series of alternating programming pulses and verify operations, with the memory cells individually locking out from further programming pulses as verified. The determination of whether the word-line is defective based on the number of programming pulses for the memory cells of a first subset of the first plurality to verify as programmed relative to the number of programming pulses for the memory cells of a second subset of the first plurality to verify as programmed, where the first and second subsets each contain multiple memory cells and are not the same.

    ADAPTING WORD LINE PULSE WIDTHS IN MEMORY SYSTEMS
    6.
    发明公开
    ADAPTING WORD LINE PULSE WIDTHS IN MEMORY SYSTEMS 有权
    适应在存储系统中字线脉冲宽度

    公开(公告)号：EP2232502A1

    公开(公告)日：2010-09-29

    申请号：EP08861986.1

    申请日：2008-12-15

    申请人： QUALCOMM Incorporated

    发明人： ABU-RAHMA, Mohamed, H. ,  YOON, Sei, Seung

    IPC分类号： G11C29/50

    CPC分类号： G11C29/50 ,  G11C7/22 ,  G11C8/08 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0407 ,  G11C2029/1202

    摘要： Systems, circuits and methods for adapting word line (WL) pulse widths used in memory systems are disclosed. One embodiment of the invention is directed to an apparatus comprising a memory system. The memory system comprises: a memory operating according to a wordline (WL) pulse with an associated WL pulse width; a built-in self-test (BIST) unit that interfaces with the memory, the BIST unit being configured to run a self-test of the internal functionality of the memory and provide a signal indicating if the memory passed or failed the self-test; and an adaptive WL control circuit that interfaces with the BIST unit and the memory, the adaptive WL control circuit being configured to adjust the WL pulse width of the memory based on the signal provided by the BIST unit.

    ASYMMETRIC STATE DETECTION FOR NON-VOLATILE STORAGE
    7.
    发明授权
    ASYMMETRIC STATE DETECTION FOR NON-VOLATILE STORAGE 有权

    公开(公告)号：EP3084769B1

    公开(公告)日：2018-09-05

    申请号：EP14815188.9

    申请日：2014-12-05

    申请人： SanDisk Technologies LLC

    发明人： PATEL, Rohan ,  KOH, Pao-Ling ,  TAM, Eugene

    IPC分类号： G11C11/56 ,  G11C16/34 ,  G11C29/02 ,  G11C29/12

    CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2211/5621

    摘要： Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.