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    SEPARATE READ AND WRITE ADDRESS DECODING IN A MEMORY SYSTEM TO SUPPORT SIMULTANEOUS MEMORY READ AND WRITE OPERATIONS
    2.
    发明公开
    SEPARATE READ AND WRITE ADDRESS DECODING IN A MEMORY SYSTEM TO SUPPORT SIMULTANEOUS MEMORY READ AND WRITE OPERATIONS 审中-公开

    公开(公告)号：EP3523804A1

    公开(公告)日：2019-08-14

    申请号：EP17768324.0

    申请日：2017-09-05

    申请人： Qualcomm Incorporated

    发明人： GARG, Manish

    IPC分类号： G11C7/10 ,  G11C8/10 ,  G11C11/419 ,  G11C11/418 ,  G11C8/08

    摘要： Memory systems that provide separate read and write address decoding to support simultaneous memory read and write operations are disclosed. Separating read and write address decoding can avoid circuit conflicts for a simultaneous memory read and write operation even if employing single port memory bit cells. The read and write addresses of respective read and write operations are separately decoded into read and write row and column selects driven to a memory array so that simultaneous read and write operations are not affected by each other. To avoid a circuit conflict for a simultaneous read and write operation, the memory system is configured to prioritize a write row select over a read row select to drive a row of memory bit cells in the memory array. In this manner, that write operation will always be successful regardless of whether the read and write row select are to the same row.

    METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL
    4.
    发明公开
    METHOD AND APPARATUS OF REDUCING LEAKAGE POWER IN MULTIPLE PORT SRAM MEMORY CELL 审中-公开
    方法和装置与多个端子的SRAM存储单元减少渗漏

    公开(公告)号：EP2761621A1

    公开(公告)日：2014-08-06

    申请号：EP12777992.4

    申请日：2012-09-30

    申请人： Qualcomm Incorporated

    发明人： PHAN, Michael ThaiThanh ,  GARG, Manish ,  HOFF, David Paul

    IPC分类号： G11C11/413

    CPC分类号： G11C11/413 ,  G11C5/148

    摘要： Systems and method for reducing leakage currents and power consumption in a memory array comprising memory cells, such as 8T SRAM cells. The memory array includes logic for dynamically placing a group of memory cells in the memory array in a reduced power state during sleep mode or inactive states of the group of memory cells, such that leakage parts are effectively eliminated. The memory array further includes logic for dynamically enabling a selected group of the memory cells during read or write access operations on the selected memory cells, wherein corresponding read or write bitlines are precharged before and after the respective rear or write operations.

    APPARATUS FOR SELECTIVE WORD-LINE BOOST ON A MEMORY CELL
    8.
    发明公开
    APPARATUS FOR SELECTIVE WORD-LINE BOOST ON A MEMORY CELL 审中-公开
    装置用于选择性字线GAIN的单元格

    公开(公告)号：EP2756500A1

    公开(公告)日：2014-07-23

    申请号：EP12769230.9

    申请日：2012-09-12

    申请人： Qualcomm Incorporated

    发明人： GARG, Manish ,  PHAN, Michael ThaiThanh

    IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C8/16 ,  G11C8/08

    摘要： Systems and methods for selectively boosting word-line (WL) voltage in a memory cell array. The method relies several embodiments to minimize energy costs associated with WL boost scheme. One embodiment generates a transient voltage boost rather than supply a DC voltage boost. The transient boost generation may be controlled on a cycle basis and can be disabled when the array is not accessed. Another embodiment allows the system to generate the transient voltage boost locally, near a WL driver and only during the cycles when it is needed. Localized boost voltage generation reduces the load capacitance that needs to be boosted to higher voltage. Another embodiment efficiently distributes the transient boost to the WL drivers.

    ADAPTIVE CLOCK GENERATORS, SYSTEMS, AND METHODS
    9.
    发明公开
    ADAPTIVE CLOCK GENERATORS, SYSTEMS, AND METHODS 有权
    自适应时钟发生器，系统和方法

    公开(公告)号：EP2514095A1

    公开(公告)日：2012-10-24

    申请号：EP10795887.8

    申请日：2010-12-14

    申请人： Qualcomm Incorporated

    发明人： GARG, Manish ,  CHAI, Chiaming ,  BRIDGES, Jeffrey Todd

    IPC分类号： H03K3/03 ,  H03K5/00

    CPC分类号： H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00215

    摘要： Adaptive clock generators, systems, and related methods than can be used to generate a clock signal for a functional circuit to avoid or reduce performance margin are disclosed. In certain embodiments, a clock generator autonomously and adaptively generates a clock signal according to a delay path(s) provided in a delay circuit(s) relating to a selected delay path(s) in the functional circuit(s). The clock generator includes a delay circuit(s) adapted to receive an input signal and delay the input signal by an amount relating to a delay path(s) of a functional circuit(s) to produce an output signal. A feedback circuit is coupled to the delay circuit(s) and responsive to the output signal, wherein the feedback circuit is adapted to generate the input signal back to the delay circuit(s) in an oscillation loop configuration. The input signal can be used to provide a clock signal to the functional circuit(s).