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    SYSTEM AND METHOD OF COUNTING LEADING ZEROS AND COUNTING LEADING ONES IN A DIGITAL SIGNAL PROCESSOR
    2.
    发明公开
    SYSTEM AND METHOD OF COUNTING LEADING ZEROS AND COUNTING LEADING ONES IN A DIGITAL SIGNAL PROCESSOR 有权
    系统和方法用于计算领先的零和数字信号处理器

    公开(公告)号：EP1896919A1

    公开(公告)日：2008-03-12

    申请号：EP06774243.7

    申请日：2006-06-27

    申请人： QUALCOMM INCORPORATED

    发明人： KOOB, Christopher Edward ,  LIANG, Jian

    IPC分类号： G06F1/00

    CPC分类号： G06F7/74 ,  G06F2207/3816

    摘要： A system and method is disclosed and includes an execution unit that can be used to count the leading zeros in a data word. During operation, the execution unit can receive a data word that has a width of 2 to the Nth power. Further, the execution unit can sign extend the data word to a temporary data word that has a width of 2 to the Mth power, wherein M is greater than N. The temporary data word can be input to a counter that has a width of 2 to the Mth power and the counter can count the leading zeros within the temporary data word to get a result.

    ZERO PIXEL CULLING FOR GRAPHICS PROCESSING
    4.
    发明公开
    ZERO PIXEL CULLING FOR GRAPHICS PROCESSING 审中-公开

    公开(公告)号：EP3326155A1

    公开(公告)日：2018-05-30

    申请号：EP16729688.8

    申请日：2016-05-26

    申请人： Qualcomm Incorporated

    发明人： DUVVURU, Nagarjuna ,  WANG, Tao ,  LIANG, Jian ,  WANG, Chunlin

    IPC分类号： G06T15/40 ,  G06T11/40

    CPC分类号： G06T15/40 ,  G06T11/40 ,  G06T15/005 ,  G06T2200/04 ,  G06T2200/12 ,  G06T2200/28

    摘要： A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.

    ADAPTIVE MEMORY ADDRESS SCANNING BASED ON SURFACE FORMAT FOR GRAPHICS PROCESSING
    8.
    发明公开
    ADAPTIVE MEMORY ADDRESS SCANNING BASED ON SURFACE FORMAT FOR GRAPHICS PROCESSING 审中-公开
    基于表面格式的图形处理自适应存储器地址扫描

    公开(公告)号：EP3289560A1

    公开(公告)日：2018-03-07

    申请号：EP16713654.8

    申请日：2016-03-02

    申请人： Qualcomm Incorporated

    发明人： LIANG, Jian ,  HUANG, Minjie ,  WANG, Chunlin

    IPC分类号： G06T1/60 ,  G06T11/40

    摘要： This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.

    CACHE DATA MIGRATION IN A MULTICORE PROCESSING SYSTEM
    9.
    发明公开
    CACHE DATA MIGRATION IN A MULTICORE PROCESSING SYSTEM 有权
    在多核处理器系统缓存中的数据迁移

    公开(公告)号：EP2880539A1

    公开(公告)日：2015-06-10

    申请号：EP13737941.8

    申请日：2013-07-01

    申请人： Qualcomm Incorporated

    发明人： LIANG, Jian ,  SHEN, Jian

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0806 ,  G06F12/0893 ,  Y02D10/13

    摘要： A method of transferring data between two caches comprises sending a first message from a first processor to a second processor indicating that data is available for transfer from a first cache associated with the first processor, requesting, from the second processor, a data transfer of the data from the first cache to a second cache associated with the second processor, transferring the data from the first cache to the second cache in response to the request, and sending a second message from the second processor to the first processor indicating that the data transfer is complete.