利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.01 秒)

    CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL)
    1.
    发明公开
    CLOCK CLEAN-UP PHASE-LOCKED LOOP (PLL) 审中-公开
    时钟净化锁相环（PLL）

    公开(公告)号：EP2345163A1

    公开(公告)日：2011-07-20

    申请号：EP09737503.4

    申请日：2009-10-08

    申请人： QUALCOMM Incorporated

    发明人： LIN, I-Hsiang ,  BROCKENBROUGH, Roger

    IPC分类号： H03L7/22 ,  H04B1/00

    CPC分类号： H03L7/07 ,  H03L7/081 ,  H03L7/0995 ,  H03L7/197 ,  H03L7/22 ,  H03L7/23 ,  H04B1/0039

    摘要： A clock clean-up phase-locked loop (PLL) that may reduce spurs and improve performance of a receiver is described. In one exemplary design, an integrated circuit includes a PLL and an analog-to-digital converter (ADC). The PLL receives a first clock signal generated with a fractional divider ratio and having spurs due to abrupt frequency jumps. The first clock signal may be generated by a fractional-N frequency synthesizer external to the integrated circuit. The PLL generates a second clock signal with an integer divider ratio and having reduced spurs. The ADC digitizes an analog baseband signal based on the second clock signal and provides digital samples. The integrated circuit may further include a low noise amplifier (LNA), which may observe less spurs coupled via the substrate of the integrated circuit due to the use of the PLL to clean up the first clock signal.

    GLOBAL NAVIGATION SATELLITE SYSTEM RECEIVER WITH FILTER BYPASS MODE FOR IMPROVED SENSITIVITY
    2.
    发明公开
    GLOBAL NAVIGATION SATELLITE SYSTEM RECEIVER WITH FILTER BYPASS MODE FOR IMPROVED SENSITIVITY 审中-公开
    接收器，具有旁路模式的全球导航卫星系统以提高灵敏度

    公开(公告)号：EP2727250A1

    公开(公告)日：2014-05-07

    申请号：EP12741134.6

    申请日：2012-06-29

    申请人： Qualcomm Incorporated

    发明人： GUDEM, Prasad Srinivasa Siva ,  ZHAO, Liang ,  LIN, I-Hsiang ,  XIONG, Zhijie ,  ASURI, Bhushan Shanti ,  HADJICHRISTOS, Aristotele

    IPC分类号： H04B1/38 ,  H04B1/52

    摘要： A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.

    摘要翻译： 有用于提高灵敏度滤波器旁路模式的全球导航卫星系统接收机的游离缺失盘。 中，提供了在宽的设备上做了包括耦合到接收器的非旁路信号路径，所述非旁路信号路径包括一个过滤器。 所以该装置包括耦合至所述接收器，所述旁路信号路径配置以绕过所述过滤器，和一个开关耦合一个旁路信号路径期间的时间间隔到天线到非旁路信号路径当信号反式上无关本地发射机mitted通过为反式mitted 与信号功率没有超过一选定阈值，并且耦合在其它时间间隔的天线到旁路信号路径。

    OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING
    7.
    发明公开
    OVERLAPPING, TWO-SEGMENT CAPACITOR BANK FOR VCO FREQUENCY TUNING 审中-公开
    OVERLAPPING，用于VCO频率调谐的两部分电容器

    公开(公告)号：EP2427963A2

    公开(公告)日：2012-03-14

    申请号：EP10718019.2

    申请日：2010-05-07

    申请人： QUALCOMM Incorporated

    发明人： ZENG, Yi ,  PAN, Tzu-Wang ,  LIN, I-Hsiang

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1253 ,  H03B5/1265 ,  H03B5/1293

    摘要： A VCO (for example, in an FM receiver) includes an LC resonant tank. The LC resonant tank includes a coarse tuning capacitor bank and a fine tuning capacitor bank. The coarse tuning capacitor bank contains a plurality of digitally controlled coarse tuning capacitor elements, each providing a first capacitance value when active. The fine tuning capacitor bank contains a plurality of digitally controlled fine tuning capacitor elements, each providing a second capacitance value when active. To address the practical problem of capacitor mismatch, capacitance overlap throughout the VCO tuning range is created by selecting the first and second capacitance values such that the capacitance value of the fine capacitor bank is greater than the first capacitance value when all of the digitally controlled fine tuning capacitor elements of the fine capacitor bank are active.

    JAMMER DETECTION BASED ADAPTIVE PLL BANDWIDTH ADJUSTMENT IN FM RECEIVER
    9.
    发明公开
    JAMMER DETECTION BASED ADAPTIVE PLL BANDWIDTH ADJUSTMENT IN FM RECEIVER 有权
    PLL带宽适配基于在FM接收器故障检测

    公开(公告)号：EP2425537A1

    公开(公告)日：2012-03-07

    申请号：EP10716691.0

    申请日：2010-04-26

    申请人： QUALCOMM Incorporated

    发明人： ZENG, Yi ,  PAN, Tzu-wang ,  LIN, I-Hsiang ,  DUNWORTH, Jeremy ,  TRIKHA, Pushp ,  APTE, Rahul

    IPC分类号： H04B1/10 ,  H03L7/107

    CPC分类号： H04B1/1027

    摘要： A frequency synthesizer within an FM receiver employs a Phase-Locked Loop (PLL) to generate a Local Oscillator (LO) signal. The LO signal is supplied to a mixer. The FM receiver also includes jammer detection functionality. If no jammer is detected, then the loop bandwidth of the PLL is set to have a relatively high value, thereby favoring suppression of in-band residual FM. If a jammer is detected, then the loop bandwidth of the PLL is set to have a relatively low value, thereby favoring suppression of out-of-band SSB phase noise. By adaptively changing loop bandwidth depending on whether a jammer is detected, performance requirements on sub-circuits within the PLL can be relaxed while still satisfying in-band residual FM and out-of-band SSB phase noise requirements. By allowing the VCO of the PLL to generate more phase noise due to the adaptive changing of loop bandwidth, VCO power consumption can be reduced.

    FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP
    10.
    发明公开
    FM TRANSMITTER AND NON-FM RECEIVER INTEGRATED ON SINGLE CHIP 审中-公开
    FM-SENDER UND NICHT-FM-EMPFÄNGER，INTEGRIERT AUF EINEM EINZIGEN CHIP

    公开(公告)号：EP2368327A2

    公开(公告)日：2011-09-28

    申请号：EP09756925.5

    申请日：2009-11-19

    申请人： QUALCOMM Incorporated

    发明人： LIN, I-Hsiang ,  PAN, Tzu-Wang ,  ZENG, Yi

    IPC分类号： H04B1/52

    CPC分类号： H04B1/525

    摘要： Exemplary embodiments include a frequency modulation (FM) transmitter and a non-FM receiver, which may be implemented on the same IC chip. The FM transmitter may include a digital FM modulator, a lowpass filter, an amplifier, and an LC tank circuit. The digital FM modulator may receive a digital input signal, perform FM modulation with the digital input signal, and provide a digital FM signal. The lowpass filter may filter the digital FM signal and provide a filtered FM signal. The amplifier may amplify the filtered FM signal and provide an output FM signal. The LC tank circuit may filter the output FM signal. The digital FM modulator may perform FM modulation by changing a variable divider ratio of a multi-modulus divider within a PLL. A delta-sigma modulator may receive the digital input signal and generate a modulator output signal used to obtain the variable divider ratio.

    摘要翻译： 示例性实施例包括可以在同一IC芯片上实现的频率调制（FM）发射机和非FM接收机。 FM发射机可以包括数字FM调制器，低通滤波器，放大器和LC谐振电路。 数字FM调制器可以接收数字输入信号，使用数字输入信号执行FM调制，并提供数字FM信号。 低通滤波器可以对数字FM信号进行滤波并提供滤波后的FM信号。 放大器可以放大滤波的FM信号并提供输出FM信号。 LC振荡电路可以对输出的FM信号进行滤波。 数字FM调制器可以通过改变PLL内的多模式分频器的可变分频比来执行FM调制。 Δ-Σ调制器可以接收数字输入信号并产生用于获得可变分频比的调制器输出信号。