专利检索 ap:("Qualcomm Incorporated") AND inv:"PANTH, Shreepad A." 第 1 页

1.

发明公开
CLOCK DISTRIBUTION NETWORK FOR 3D INTEGRATED CIRCUIT 审中-公开
标题翻译：时钟分配网络是集成电路3D

公开(公告)号：EP2926280A1

公开(公告)日：2015-10-07

申请号：EP13811061.4

申请日：2013-11-27

申请人： Qualcomm Incorporated

发明人： SAMADI, Kambiz , PANTH, Shreepad A. , XIE, Jing , DU, Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 , G06F1/32 , G06F1/3287 , G06F17/5045 , G06F17/505 , G06F17/5068 , G06F17/5077 , G06F2217/62 , G11C5/14 , H01L23/5226 , H01L2924/0002 , H03K19/0008 , H01L2924/00

摘要： Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

2.

发明公开
HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO 审中-公开
标题翻译：用封闭点，集成电路和方法，其会透过一个硬宏HART MACRO

公开(公告)号：EP2920719A1

公开(公告)日：2015-09-23

申请号：EP13802156.3

申请日：2013-11-14

申请人： Qualcomm Incorporated

发明人： SAMADI, Kambiz , PANTH, Shreepad A. , DU, Yang , GILMORE, Robert P.

IPC分类号： G06F17/50

CPC分类号： H01L23/49827 , G06F17/5068 , H01L21/76802 , H01L2924/0002 , H01L2924/00

摘要： A hard macro (208, 308, 500) includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias (216, 318, 404) extending through the hard macro thickness from the top to the bottom. Also an integrated circuit (200, 300) having a top layer (202, 302), a bottom layer (210, 310) and at least one middle layer (206, 306), the top layer (202, 302) including a top layer conductive trace, the middle layer including a hard macro (208, 308) and the bottom layer (210, 310) including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via (216, 318, 404) extending through the hard macro (208, 308, 500).