公开(公告)号：EP3513496A1

公开(公告)日：2019-07-24

申请号：EP17745559.9

申请日：2017-07-12

申请人： Qualcomm Incorporated

发明人： SAMSON, Giby ,  PU, Yu ,  DU, Yang

IPC分类号： H03K19/003 ,  H01L27/06 ,  H03K3/03

公开(公告)号：EP3022769A1

公开(公告)日：2016-05-25

申请号：EP14750058.1

申请日：2014-07-15

申请人： Qualcomm Incorporated

发明人： KAMAL, Pratyush ,  DU, Yang

IPC分类号： H01L27/06 ,  H03K3/3562

CPC分类号： H03K3/0372 ,  G06F17/5068 ,  H01L27/0688 ,  H03K3/35625

摘要： Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

公开(公告)号：EP2965359A1

公开(公告)日：2016-01-13

申请号：EP14715477.7

申请日：2014-03-05

申请人： Qualcomm Incorporated

发明人： DU, Yang

IPC分类号： H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC分类号： H01L23/48 ,  B82Y10/00 ,  B82Y99/00 ,  H01L21/76254 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L2924/0002 ,  Y10S977/762 ,  H01L2924/00

摘要： Three-dimensional integrated circuit comprising top tier nanowire transistors formed on a bottom tier of CMOS transistors, with inter-tier vias, intra-tier vias, and metal layers to connect together the various CMOS transistors and nanowire transistors. The top tier first begins as lightly doped regions on a first wafer, with an oxide layer formed over the regions. Hydrogen ion implantation forms a cleavage interface. The first wafer is flipped and oxide bonded to a second wafer having CMOS devices, and the cleavage interface is thermally activated so that a portion of the lightly doped regions remains bonded to the bottom tier. Nanowire transistors are formed in the top tier layer. The sources and drains for the top tier nanowire transistors are formed by in-situ doping during epitaxial growth. After oxide bonding, the remaining process steps are performed at low temperatures so as not to damage the metal interconnects.

公开(公告)号：EP2926280A1

公开(公告)日：2015-10-07

申请号：EP13811061.4

申请日：2013-11-27

申请人： Qualcomm Incorporated

发明人： SAMADI, Kambiz ,  PANTH, Shreepad A. ,  XIE, Jing ,  DU, Yang

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

摘要： Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

公开(公告)号：EP2676295A1

公开(公告)日：2013-12-25

申请号：EP12710002.2

申请日：2012-02-17

申请人： Qualcomm Incorporated

发明人： DU, Yang ,  APARIN, Vladimir ,  GILMORE, Robert

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/42384 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624 ,  H01L29/78645

摘要： High-speed high-power semiconductor devices are disclosed. In an exemplary design, a high-speed high-power semiconductor device includes a source, a drain to provide an output signal, and an active gate to receive an input signal. The semiconductor device further includes at least one field gate located between the active gate and the drain, at least one shallow trench isolation (STI) strip formed transverse to the at least one field gate, and at least one drain active strip formed parallel to, and alternating with, the at least one STI strip. The semiconductor device may be modeled by a combination of an active FET and a MOS varactor. The active gate controls the active FET, and the at least one field gate controls the MOS varactor. The semiconductor device has a low on resistance and can handle a high voltage.

公开(公告)号：EP3676764A1

公开(公告)日：2020-07-08

申请号：EP18773318.3

申请日：2018-09-01

申请人： Qualcomm Incorporated

发明人： PU, Yu ,  DU, Yang

IPC分类号： G06N3/063 ,  G06F1/32 ,  G06N3/04 ,  G06N3/08 ,  G11C11/00 ,  G11C11/16 ,  G11C11/54 ,  G11C13/00 ,  H01L25/18 ,  H01L25/00

公开(公告)号：EP3060967B1

公开(公告)日：2019-03-06

申请号：EP14790943.6

申请日：2014-10-15

申请人： Qualcomm Incorporated

发明人： KAMAL, Pratyush ,  DU, Yang ,  SAMADI, Kambiz

IPC分类号： G06F1/32 ,  H01L27/06

公开(公告)号：EP2926279B1

公开(公告)日：2018-06-13

申请号：EP13811060.6

申请日：2013-11-27

申请人： Qualcomm Incorporated

发明人： XIE, Jing ,  DU, Yang

IPC分类号： G06F1/32

CPC分类号： G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  Y02D10/171 ,  H01L2924/00

摘要： Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

公开(公告)号：EP3256969A1

公开(公告)日：2017-12-20

申请号：EP16703403.2

申请日：2016-01-20

申请人： Qualcomm Incorporated

发明人： LIM, Sung Kyu ,  SAMADI, Kambiz ,  DU, Yang

IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

摘要： An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

公开(公告)号：EP3060967A1

公开(公告)日：2016-08-31

申请号：EP14790943.6

申请日：2014-10-15

申请人： Qualcomm Incorporated

发明人： KAMAL, Pratyush ,  DU, Yang ,  SAMADI, Kambiz

IPC分类号： G06F1/32 ,  H01L27/06

CPC分类号： G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.