公开(公告)号：EP3039717B1

公开(公告)日：2018-12-12

申请号：EP14759424.6

申请日：2014-08-22

申请人： Qualcomm Incorporated

发明人： VAHID FAR, Mohammad, B. ,  KHALILI, Alireza ,  WANG, Cheng-Han ,  CHEN, Phoebe, Peihong

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02 ,  H02M3/00 ,  H02M3/18

CPC分类号： H01L29/94 ,  H01L27/0805 ,  H01L27/0811 ,  H02M3/00 ,  H02M3/18

摘要： A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

公开(公告)号：EP3039717A1

公开(公告)日：2016-07-06

申请号：EP14759424.6

申请日：2014-08-22

申请人： Qualcomm Incorporated

发明人： VAHID FAR, Mohammad, B. ,  KHALILI, Alireza ,  WANG, Cheng-Han ,  CHEN, Phoebe, Peihong

IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02

CPC分类号： H01L29/94 ,  H01L27/0805 ,  H01L27/0811 ,  H02M3/00 ,  H02M3/18

摘要： A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

摘要翻译： 公开了具有改善的线性度的MOS电容器。 在示例性实施例中，一种装置包括主分支，该主分支包括具有与反向极性串联连接的第一电容器对的第一信号路径和具有与反向极性串联连接的第二电容器对的第二信号路径，第一和第二信号路径 并联连接 该装置还包括辅助支路，该辅助支路包括至少一个信号路径，该至少一个信号路径具有至少一个与反向极性串联连接并与主支路并联连接的电容器对。 在示例性实施例中，电容器是MOS电容器。