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    SUBTHRESHOLD METAL OXIDE SEMICONDUCTOR FOR LARGE RESISTANCE
    3.
    发明公开
    SUBTHRESHOLD METAL OXIDE SEMICONDUCTOR FOR LARGE RESISTANCE 审中-公开
    亚阈值金属氧化物半导体用于大电阻

    公开(公告)号：EP3231088A1

    公开(公告)日：2017-10-18

    申请号：EP15797226.6

    申请日：2015-11-06

    申请人： Qualcomm Incorporated

    发明人： TAGHIVAND, Mazhareddin ,  RAJAVI, Yashar ,  KHALILI, Alireza

    IPC分类号： H03H11/24

    摘要： Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.

    摘要翻译： 本公开的某些方面一般涉及产生大的电阻。 一个示例性电路通常包括具有栅极，与电路的第一节点214连接的源极，以及与电路的第二节点216连接的漏极的第一晶体管210,220。 该电路还可以包括连接在第一晶体管的栅极和源极之间的电压限制器件224,226，其中该器件如果正向偏置，则被配置为限制第一晶体管的栅极 - 源极电压，使得 第一晶体管在亚阈值区域中操作。 该电路还可以包括第二晶体管212,222，该第二晶体管212,222被配置为利用电流对电压限制器件进行偏置，其中第二晶体管的漏极与第一晶体管的栅极连接，第二晶体管的栅极与 第一节点，并且第二晶体管的源极与电势连接。

    DIFFERENTIAL CRYSTAL OSCILLATOR CIRCUIT
    4.
    发明授权
    DIFFERENTIAL CRYSTAL OSCILLATOR CIRCUIT 有权

    公开(公告)号：EP3172835B1

    公开(公告)日：2018-10-17

    申请号：EP15732148.0

    申请日：2015-06-16

    申请人： Qualcomm Incorporated

    发明人： RAJAVI, Yashar ,  KAVOUSIAN, Amirpouya ,  KHALILI, Alireza ,  VAHID FAR, Mohammad Bagher ,  KOMIJANI, Abbas

    IPC分类号： H03B5/36 ,  H03B5/06

    CPC分类号： H03B5/364 ,  H03B5/06 ,  H03B5/36 ,  H03B2200/004 ,  H03B2200/0094

    摘要： A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (MOSFET) diodes, each MOSFET diode including a resistor connected between gate and drain terminals, wherein the first MOSFET diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second MOSFET diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.

    INCREASED SYNTHESIZER PERFORMANCE IN CARRIER AGGREGATION/MULTIPLE-INPUT, MULTIPLE-OUTPUT SYSTEMS
    5.
    发明公开
    INCREASED SYNTHESIZER PERFORMANCE IN CARRIER AGGREGATION/MULTIPLE-INPUT, MULTIPLE-OUTPUT SYSTEMS 有权
    载波汇聚/多输入，多输出系统中合成器性能的提高

    公开(公告)号：EP3192181A1

    公开(公告)日：2017-07-19

    申请号：EP15754075.8

    申请日：2015-08-11

    申请人： Qualcomm Incorporated

    发明人： KHALILI, Alireza ,  TAGHIVAND, Mazhareddin ,  KEERTI, Arvind

    IPC分类号： H04B1/00

    CPC分类号： H03L7/099 ,  H03B5/1212 ,  H04B1/005 ,  H04B1/0064

    摘要： Certain aspects of the present disclosure provide methods and apparatus for using multiple voltage-controlled oscillators (VCOs) to increase frequency synthesizer performance, such as in stringent multiple-input, multiple-output (MIMO) modes. One example apparatus capable of generating oscillating signals generally includes a first VCO, a second VCO, and connection circuitry configured to connect the second VCO in parallel with the first VCO if a phase-locked loop (PLL) associated with the second VCO is idle.

    摘要翻译： 本公开的某些方面提供了用于使用多个压控振荡器（VCO）来提高频率合成器性能的方法和设备，诸如在严格的多输入多输出（MIMO）模式中。 能够产生振荡信号的一个示例装置通常包括第一VCO，第二VCO和被配置为如果与第二VCO相关联的锁相环（PLL）空闲则将第二VCO与第一VCO并联连接的连接电路。

    ARCHITECTURE TO REJECT NEAR END BLOCKERS AND TRANSMIT LEAKAGE
    6.
    发明公开
    ARCHITECTURE TO REJECT NEAR END BLOCKERS AND TRANSMIT LEAKAGE 有权
    抵制近端阻塞和传输泄漏的架构

    公开(公告)号：EP3170263A1

    公开(公告)日：2017-05-24

    申请号：EP15739371.1

    申请日：2015-06-17

    申请人： Qualcomm Incorporated

    发明人： VAHID FAR, Mohammad Bagher ,  WANG, Cheng-Han ,  RICHMOND, Jesse Aaron ,  NGUYEN, Thinh Cat ,  KOMIJANI, Abbas ,  RAJAVI, Yashar ,  KHALILI, Alireza

    IPC分类号： H04B1/10 ,  H03H11/04 ,  H03H11/12 ,  H04B1/525

    CPC分类号： H03H11/0433 ,  H03H11/1252 ,  H04B1/109 ,  H04B1/525

    摘要： A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.

    摘要翻译： 提供了一种用于最小化发射信号干扰的方法和设备。 该方法包括以下步骤：接收信号并放大接收到的信号。 接收到的信号然后与中频信号混合以获得基带调制信号。 基带调制信号首先在RC滤波器中进行滤波。 然后将得到的信号除以预选的量，并将第一分频部分发送到双二阶滤波器的主路径，其产生第一级双二阶滤波信号。 分频信号的第二部分被发送到双二阶滤波器的辅助路径，并产生第二滤波信号。 然后将第一和第二信号重新组合并发送到双二阶滤波器的第二阶段，在那里进行进一步滤波。

    LOW-POWER RX SYNTHESIZER SHARING TX HARDWARE
    7.
    发明公开
    LOW-POWER RX SYNTHESIZER SHARING TX HARDWARE 审中-公开
    低功耗RX合成器共享TX硬件

    公开(公告)号：EP3251220A1

    公开(公告)日：2017-12-06

    申请号：EP15820967.6

    申请日：2015-12-16

    申请人： Qualcomm Incorporated

    发明人： RAJAVI, Yashar ,  KHALILI, Alireza ,  ADNAN, Muhammad

    IPC分类号： H04B1/403 ,  H04W52/02

    CPC分类号： H04W52/028 ,  H04B1/403 ,  Y02D70/00 ,  Y02D70/142 ,  Y02D70/40

    摘要： An analog front-end (AFE) for a communications device includes a low-power frequency synthesizer with reduced footprint. The AFE includes a first frequency synthesizer and a second frequency synthesizer. The first frequency synthesizer is coupled to a transmit (TX) chain and to a receive (RX) chain of the AFE. The first frequency synthesizer is to generate a first local oscillator (LO) signal for transmitting or receiving carrier signals when the device is in a normal operating mode. The second frequency synthesizer is coupled to the RX chain and shares one or more components of the TX chain. The second frequency synthesizer is to utilize the one or more shared components to generate a second LO signal for receiving carrier signals when the device operates in a low-power mode. For example, the one or more shared components may include a voltage source and/or one or more inductors.

    DIFFERENTIAL CRYSTAL OSCILLATOR CIRCUIT
    8.
    发明公开
    DIFFERENTIAL CRYSTAL OSCILLATOR CIRCUIT 审中-公开
    差分晶体振荡器电路

    公开(公告)号：EP3172835A1

    公开(公告)日：2017-05-31

    申请号：EP15732148.0

    申请日：2015-06-16

    申请人： Qualcomm Incorporated

    发明人： RAJAVI, Yashar ,  KAVOUSIAN, Amirpouya ,  KHALILI, Alireza ,  VAHID FAR, Mohammad Bagher ,  KOMIJANI, Abbas

    IPC分类号： H03B5/36 ,  H03B5/06

    CPC分类号： H03B5/364 ,  H03B5/06 ,  H03B5/36 ,  H03B2200/004 ,  H03B2200/0094

    摘要： A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (MOSFET) diodes, each MOSFET diode including a resistor connected between gate and drain terminals, wherein the first MOSFET diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second MOSFET diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.

    摘要翻译： 一种差分晶体振荡器电路，包括：第一和第二输出端; 交叉耦合振荡单元，其包括交叉耦合到第一和第二输出端子的第一和第二晶体管; 第一和第二金属氧化物半导体场效应晶体管（MOSFET）二极管，每个MOSFET二极管包括连接在栅极和漏极端子之间的电阻器，其中第一MOSFET二极管耦合到第一晶体管以在低频和高频下提供低阻抗负载 - 向所述第一晶体管施加较高频率的阻抗负载，其中所述第二MOSFET二极管耦合到所述第二晶体管，以向所述第二晶体管提供低频下的低阻抗负载和更高频率下的高阻抗负载; 以及耦合在第一和第二输出端之间以建立振荡频率的参考谐振器。

    METAL OXIDE SEMICONDUCTOR (MOS) CAPACITOR WITH IMPROVED LINEARITY
    9.
    发明公开
    METAL OXIDE SEMICONDUCTOR (MOS) CAPACITOR WITH IMPROVED LINEARITY 审中-公开
    METALLOXIDHALBLEITER（MOS）-KONDENSATOR MIT VERBESSERTERLINEARITÄT

    公开(公告)号：EP3039717A1

    公开(公告)日：2016-07-06

    申请号：EP14759424.6

    申请日：2014-08-22

    申请人： Qualcomm Incorporated

    发明人： VAHID FAR, Mohammad, B. ,  KHALILI, Alireza ,  WANG, Cheng-Han ,  CHEN, Phoebe, Peihong

    IPC分类号： H01L27/08 ,  H01L23/522 ,  H01L29/94 ,  H01L49/02

    CPC分类号： H01L29/94 ,  H01L27/0805 ,  H01L27/0811 ,  H02M3/00 ,  H02M3/18

    摘要： A MOS capacitor with improved linearity is disclosed. In an exemplary embodiment, an apparatus includes a main branch comprising a first signal path having a first capacitor pair connected in series with reversed polarities and a second signal path having a second capacitor pair connected in series with reversed polarities, the first and second signal paths connected in parallel. The apparatus also includes an auxiliary branch comprising at least one signal path having at least one capacitor pair connected in series with reversed polarities and connected in parallel with the main branch. In an exemplary embodiment, the capacitors are MOS capacitors.

    摘要翻译： 公开了具有改善的线性度的MOS电容器。 在示例性实施例中，一种装置包括主分支，该主分支包括具有与反向极性串联连接的第一电容器对的第一信号路径和具有与反向极性串联连接的第二电容器对的第二信号路径，第一和第二信号路径 并联连接 该装置还包括辅助支路，该辅助支路包括至少一个信号路径，该至少一个信号路径具有至少一个与反向极性串联连接并与主支路并联连接的电容器对。 在示例性实施例中，电容器是MOS电容器。