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公开(公告)号：EP3143622B1
公开(公告)日：2018-10-03
申请号：EP15730011.2
申请日：2015-06-04
IPC分类号： G11C8/14 , G11C11/412 , G11C11/419 , G11C7/20
CPC分类号： G11C11/419 , G11C5/02 , G11C7/00 , G11C7/20 , G11C8/14 , G11C8/16 , G11C11/412 , G11C11/417
摘要： A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.
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2.发明授权SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN 有权SRAM读缓冲器具有降低的感测延迟和改进的感测裕量
公开(公告)号：EP3028281B1
公开(公告)日：2017-12-20
申请号：EP14748067.7
申请日：2014-07-21
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G06F17/5072 , G11C8/16 , G11C11/412
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3.发明公开SRAM READ BUFFER WITH REDUCED SENSING DELAY AND IMPROVED SENSING MARGIN 有权SRAM-LESEPUFFER MIT REDUZIERTERMESSVERZÖGERUNGUNDERHÖHTERMESSMARGE
公开(公告)号：EP3028281A1
公开(公告)日：2016-06-08
申请号：EP14748067.7
申请日：2014-07-21
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G06F17/5072 , G11C8/16 , G11C11/412
摘要： A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.
摘要翻译： 一种器件包括静态随机存取存储器（SRAM）单元和耦合到SRAM单元的输出的读缓冲器。 读缓冲器包括一个反相器和一个开关。 反相器的输入响应于SRAM单元的输出。 开关的控制端子响应于逆变器的输出。
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公开(公告)号：EP3198607B1
公开(公告)日：2018-12-26
申请号：EP15772122.6
申请日：2015-09-15
IPC分类号： G11C11/419 , G11C11/412
CPC分类号： G11C11/419 , G11C11/412
摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.
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5.发明公开SEVEN-TRANSISTOR SRAM BITCELL WITH TRANSMISSION GATE PROVIDING REDUCED READ DISTURBANCE 有权带传输门的7位晶体管SRAM BITCELL提供读取干扰减少
公开(公告)号：EP3198607A1
公开(公告)日：2017-08-02
申请号：EP15772122.6
申请日：2015-09-15
IPC分类号： G11C11/412
CPC分类号： G11C11/419 , G11C11/412
摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.
摘要翻译： 系统和方法涉及包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器的第七晶体管静态随机存取存储器（7T SRAM）位单元，以及具有第一反相器 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间选择性地将第一存储节点耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点从 在读取操作期间第一上拉晶体管和第一下拉晶体管的栅极。 7T SRAM位单元可以通过耦合到第一存储节点的存取晶体管读取或写入。
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6.发明授权STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS 有权静态随机访问存储器（SRAM），具有读取首选的单元结构，写入驱动器，相关系统和方法
公开(公告)号：EP2948954B1
公开(公告)日：2018-04-04
申请号：EP14702731.2
申请日：2014-01-22
发明人： JUNG, Seong-Ook , YANG, Younghwi , YANG, Bin , WANG, Zhongze , YEAP, Choh fei
IPC分类号： G11C11/419 , G11C11/412 , G11C11/417
CPC分类号： G11C11/412 , G11C11/417 , G11C11/419 , H01L27/0207 , H01L27/1104 , Y10T29/41
摘要： Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.
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公开(公告)号：EP3143622A1
公开(公告)日：2017-03-22
申请号：EP15730011.2
申请日：2015-06-04
IPC分类号： G11C8/14 , G11C11/412 , G11C7/20
CPC分类号： G11C11/419 , G11C5/02 , G11C7/00 , G11C7/20 , G11C8/14 , G11C8/16 , G11C11/412 , G11C11/417
摘要： A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.
摘要翻译： 静态随机存取存储器（SRAM）存储单元包括一对交叉耦合的反相器和耦合到该对交叉耦合的反相器的第一反相器的第一节点的选通晶体管。 门控晶体管的栅极耦合到第一字线。 门控晶体管被配置为响应于第一字线信号选择性地将位线耦合到第一反相器的第一节点。 第一反相器具有耦合到第二字线的第二节点。 第一个字线和第二个字线都是独立可控的。
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8.发明公开STATIC RANDOM ACCESS MEMORIES (SRAM) WITH READ-PREFERRED CELL STRUCTURES, WRITE DRIVERS, RELATED SYSTEMS, AND METHODS 有权静态随机存取存储器（SRAM）伴读优先小区的结构，编写驱动程序，相关系统和方法
公开(公告)号：EP2948954A1
公开(公告)日：2015-12-02
申请号：EP14702731.2
申请日：2014-01-22
发明人： JUNG, Seong-Ook , YANG, Younghwi , YANG, Bin , WANG, Zhongze , YEAP, Choh fei
IPC分类号： G11C11/412 , G11C11/417
CPC分类号： G11C11/412 , G11C11/417 , G11C11/419 , H01L27/0207 , H01L27/1104 , Y10T29/41
摘要： Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.
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