公开(公告)号：EP3028281B1

公开(公告)日：2017-12-20

申请号：EP14748067.7

申请日：2014-07-21

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/412

CPC分类号： G11C11/419 ,  G06F17/5072 ,  G11C8/16 ,  G11C11/412

公开(公告)号：EP3028281A1

公开(公告)日：2016-06-08

申请号：EP14748067.7

申请日：2014-07-21

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/412

CPC分类号： G11C11/419 ,  G06F17/5072 ,  G11C8/16 ,  G11C11/412

摘要： A device includes a static random access memory (SRAM) cell and a read buffer coupled to an output of the SRAM cell. The read buffer includes an inverter and a switch. An input of the inverter is responsive to the output of the SRAM cell. A control terminal of the switch is responsive to an output of the inverter.

摘要翻译： 一种器件包括静态随机存取存储器（SRAM）单元和耦合到SRAM单元的输出的读缓冲器。 读缓冲器包括一个反相器和一个开关。 反相器的输入响应于SRAM单元的输出。 开关的控制端子响应于逆变器的输出。

公开(公告)号：EP3198607B1

公开(公告)日：2018-12-26

申请号：EP15772122.6

申请日：2015-09-15

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/419 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

公开(公告)号：EP3198607A1

公开(公告)日：2017-08-02

申请号：EP15772122.6

申请日：2015-09-15

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： G11C11/412

CPC分类号： G11C11/419 ,  G11C11/412

摘要： Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

摘要翻译： 系统和方法涉及包括具有第一上拉晶体管，第一下拉晶体管和第一存储节点的第一反相器的第七晶体管静态随机存取存储器（7T SRAM）位单元，以及具有第一反相器 第二上拉晶体管，第二下拉晶体管和第二存储节点。 第二存储节点耦合到第一上拉晶体管和第一下拉晶体管的栅极。 传输门被配置为在写入操作，待机模式和保持模式期间选择性地将第一存储节点耦合到第二上拉晶体管和第二下拉晶体管的栅极，并且选择性地将第一存储节点从 在读取操作期间第一上拉晶体管和第一下拉晶体管的栅极。 7T SRAM位单元可以通过耦合到第一存储节点的存取晶体管读取或写入。

公开(公告)号：EP3143622B1

公开(公告)日：2018-10-03

申请号：EP15730011.2

申请日：2015-06-04

申请人： Qualcomm Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

发明人： JUNG, Seong-Ook ,  YANG, Younghwi ,  SONG, Stanley Seungchul ,  YEAP, Choh Fei ,  WANG, Zhongze

IPC分类号： G11C8/14 ,  G11C11/412 ,  G11C11/419 ,  G11C7/20

CPC分类号： G11C11/419 ,  G11C5/02 ,  G11C7/00 ,  G11C7/20 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417

摘要： A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

公开(公告)号：EP3278365A1

公开(公告)日：2018-02-07

申请号：EP16705652.2

申请日：2016-02-03

申请人： Qualcomm Incorporated

发明人： SONG, Stanley Seungchul ,  XU, Jeffrey Junhao ,  RIM, Kern ,  YANG, Da ,  ZHU, John Jianhong ,  BAO, Junjing ,  MOJUMDER, Niladri Narayan ,  MACHKAOUTSAN, Vladimir ,  BADAROGLU, Mustafa ,  YEAP, Choh Fei

IPC分类号： H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/764

CPC分类号： H01L21/76897 ,  H01L21/32139 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

摘要： A fin-type semiconductor device includes a gate structure and a source/drain structure. The fin-type semiconductor device also includes a gate hardmask structure coupled to the gate structure. The gate hardmask structure comprises a first material. The fin-type semiconductor device further includes a source/drain hardmask structure coupled to the source/drain structure. The source/drain hardmask structure comprises a second material.

公开(公告)号：EP3275013A1

公开(公告)日：2018-01-31

申请号：EP16710629.3

申请日：2016-03-09

申请人： Qualcomm Incorporated

发明人： GENG, Chunqi ,  YEAP, Choh Fei ,  SONG, Stanley Seungchul

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  G06F17/5063 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092

摘要： A semiconductor chip includes a circuit block. The circuit block includes a first transistor(s) having an enhanced first performance characteristic different from a second performance characteristic of a second transistor(s) of the circuit block. The circuit block also includes a marker layer to identify the first transistor(s).

公开(公告)号：EP3248217A1

公开(公告)日：2017-11-29

申请号：EP16704729.9

申请日：2016-01-20

申请人： Qualcomm Incorporated

发明人： XU, Jeffrey Junhao ,  BAO, Junjing ,  ZHU, John Jianhong ,  SONG, Stanley Seungchul ,  MOJUMDER, Niladri Narayan ,  YEAP, Choh Fei

IPC分类号： H01L23/00

CPC分类号： H01L23/53223 ,  B29C64/386 ,  B33Y50/02 ,  G05B19/418 ,  G05B2219/45031 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76871 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53219 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit device includes a first metal layer including aluminum. The integrated circuit device includes a second metal layer including an interconnect structure. The interconnect structure includes a layer of first material including aluminum. The integrated circuit device includes an inter-diffusion layer that includes aluminum. The inter-diffusion layer is proximate to the first metal layer and proximate to the layer of first material including aluminum. The integrated circuit device includes a self-forming barrier layer that includes aluminum. The self-forming barrier layer is proximate to a dielectric layer and proximate to the layer of first material including aluminum.

公开(公告)号：EP3186831A1

公开(公告)日：2017-07-05

申请号：EP15745707.8

申请日：2015-07-23

申请人： Qualcomm Incorporated

发明人： MOJUMDER, Niladri ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： H01L27/11 ,  H01L29/10 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C11/405 ,  G11C11/409 ,  G11C11/412 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1054

摘要： A static random access memory (SRAM) circuit includes a write port and a read port coupled to the write port. The read port includes a read bit line and a first p-type metal oxide semiconductor (PMOS) transistor having a silicon germanium (SiGe) channel. The read port also includes a second PMOS transistor having a second SiGe channel, where the second PMOS transistor is coupled to the first PMOS transistor.

摘要翻译： 静态随机存取存储器（SRAM）电路包括写入端口和耦合到写入端口的读取端口。 读取端口包括读取位线和具有硅锗（SiGe）沟道的第一p型金属氧化物半导体（PMOS）晶体管。 读取端口还包括具有第二SiGe沟道的第二PMOS晶体管，其中第二PMOS晶体管耦合到第一PMOS晶体管。

公开(公告)号：EP3146564A1

公开(公告)日：2017-03-29

申请号：EP15719395.4

申请日：2015-04-20

申请人： Qualcomm Incorporated

发明人： MOJUMDER, Niladri ,  SONG, Stanley Seungchul ,  WANG, Zhongze ,  YEAP, Choh Fei

IPC分类号： H01L27/02 ,  G11C11/412 ,  H01L27/11

CPC分类号： H01L29/401 ,  H01L27/0207 ,  H01L27/1104 ,  H01L29/161

摘要： Methods and apparatus directed toward a high density static random access memory (SRAM) array having advanced metal patterning are provided. In an example, provided is a method for fabricating an SRAM. The method includes forming, using a self-aligning double patterning (SADP) technique, a plurality of substantially parallel first metal lines oriented in a first direction in a first layer. The method also includes etching the substantially parallel first metal lines, using a cut mask, in a second direction substantially perpendicular to the first direction, to separate the substantially parallel first metal lines into a plurality of islands having first respective sides that are aligned in the first direction and second respective sides that are aligned the second direction. The method also includes forming, in a second layer, a plurality of second metal lines oriented in the first direction.

摘要翻译： 提供了针对具有高级金属图案化的高密度静态随机存取存储器（SRAM）阵列的方法和装置。 在一个示例中，提供了一种用于制造SRAM的方法。 该方法包括使用自对准双图案化（SADP）技术形成在第一层中沿第一方向定向的多个基本平行的第一金属线。 该方法还包括在基本上垂直于第一方向的第二方向上使用切割掩模蚀刻基本上平行的第一金属线，以将基本上平行的第一金属线分离成多个岛，该岛具有在第 第一方向和第二方向对准第二方向。 该方法还包括在第二层中形成沿第一方向定向的多个第二金属线。