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公开(公告)号:EP3076431A4
公开(公告)日:2017-08-09
申请号:EP14865393
申请日:2014-11-26
申请人: ROHM CO LTD
发明人: NAGAO KATSUHISA , KAWAMOTO NORIAKI
IPC分类号: H01L27/04 , H01L21/822 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号: H01L27/11898 , H01L23/528 , H01L23/53214 , H01L23/53219 , H01L23/53228 , H01L23/53233 , H01L27/11807 , H01L27/11896 , H01L29/0615 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/7395 , H01L29/7397 , H01L29/78 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2027/11866
摘要: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.
摘要翻译: 制造包括SiC外延层(28),在SiC外延层(28)中形成的多个晶体管单元(18)并且通过预定控制进行开/关控制的半导体器件(1) 电压;栅极电极(19),其在半导体装置(1)处于导通状态时与形成有沟道的晶体管单元(18)的沟道区域(32)相对;栅极金属(44) 暴露在最外表面处以与外部电连接并且在与栅电极(19)物理分离的同时电连接到栅电极(19),以及内置电阻器(21),其由多晶硅制成并且 其设置在栅极金属(44)下方以将栅极金属(44)和栅极电极(19)电连接在一起。
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公开(公告)号:EP3144975A4
公开(公告)日:2018-03-14
申请号:EP15793063
申请日:2015-05-15
申请人: ROHM CO LTD
发明人: NAGAO KATSUHISA , ABE HIDETOSHI
IPC分类号: H01L29/78 , H01L23/31 , H01L29/06 , H01L29/16 , H01L29/47 , H01L29/739 , H01L29/872
CPC分类号: H01L29/1608 , H01L23/3171 , H01L23/535 , H01L23/60 , H01L29/0615 , H01L29/0619 , H01L29/36 , H01L29/4236 , H01L29/47 , H01L29/51 , H01L29/739 , H01L29/78 , H01L29/872
摘要: According to the present invention, a semiconductor device includes a first conductivity type SiC layer, an electrode that is selectively formed upon the SiC layer, and an insulator that is formed upon the SiC layer and that extends to a timing region that is set at an end part of the SiC layer. The insulator includes an electrode lower insulating film that is arranged below the electrode, and an organic insulating layer that is arranged so as to cover the electrode lower insulating film. The length (A) of the interval wherein the organic insulating layer contacts the SiC layer is 40 µm or more, and the lateral direction distance (B) along the electrode lower insulating layer between the electrode and SiC layer is 40 µm or more.
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公开(公告)号:EP2618380A4
公开(公告)日:2015-05-13
申请号:EP11825229
申请日:2011-09-15
申请人: ROHM CO LTD
发明人: OKUMURA KEIJI , MIURA MINEO , NAGAO KATSUHISA , MITANI SHUHEI
IPC分类号: H01L29/78 , H01L21/336 , H01L29/12
CPC分类号: H01L29/7827 , H01L21/046 , H01L21/049 , H01L29/045 , H01L29/0619 , H01L29/0696 , H01L29/1608 , H01L29/42368 , H01L29/45 , H01L29/518 , H01L29/66068 , H01L29/66666 , H01L29/7802 , H01L29/7811
摘要: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.
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