公开(公告)号：EP4202977B1

公开(公告)日：2024-07-24

申请号：EP22214363.8

申请日：2022-12-16

IPC分类号： H01L21/285

CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L21/76856 ,  H01L21/76843

公开(公告)号：EP4391081A1

公开(公告)日：2024-06-26

申请号：EP23218845.8

申请日：2023-12-20

申请人： Commissariat à l'énergie atomique et aux énergies alternatives

发明人： BARRAUD, Sylvain ,  COQUAND, Rémi ,  REBOH, Shay

IPC分类号： H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L21/336 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/45 ,  H01L29/775 ,  H01L29/16

CPC分类号： H01L29/0673 ,  H01L29/0847 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/45 ,  H01L29/775 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/1606 ,  H01L29/0653 ,  H10B53/30 ,  H10B12/03 ,  H10B12/05 ,  H01L29/78696

摘要： Dispositif microélectronique (100) comprenant :
- une couche de semi-conducteur (120) semi-conductrice dont plusieurs premières zones (122) sont superposées et forment un canal ;
- une grille de commande électrostatique (110) et une couche (112) de diélectrique de grille ou une couche (112) mémoire ferroélectrique dont des parties soient chacune disposée entre une partie (106, 108) de la grille et l'une des premières zones ;
- des espaceurs diélectriques (114) disposés contre des flancs de la grille ;
- des régions de source (116) / drain (118) couplées électriquement aux premières zones par des deuxièmes zones (124) de la couche de semi-conducteur s'étendant entre les régions de source / drain et les espaceurs, et/ou entre un substrat (102) et chacune des régions de source / drain ;
et dans lequel les deuxièmes zones ne sont pas disposées directement contre la grille et forment, avec les premières zones, une couche continue.

公开(公告)号：EP2248178B1

公开(公告)日：2018-10-10

申请号：EP09706248.3

申请日：2009-01-14

申请人： Kabushiki Kaisha Toshiba

发明人： SUZUKI, Takuma ,  KONO, Hiroshi ,  SHINOHE, Takashi

IPC分类号： H01L29/78 ,  H01L29/739 ,  H01L29/417 ,  H01L29/36 ,  H01L21/336 ,  H01L21/04 ,  H01L29/423 ,  H01L29/45 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7816

摘要： According to the embodiment, a semiconductor device includes an SiC substrate of a first or second conductivity type. An SiC layer of the first conductivity type is formed on a front surface of the substrate, a first SiC region of the second conductivity type is formed on the SiC layer, a second SiC region of the first conductivity type is formed within a surface of the first SiC region, a gate dielectric is continuously formed on the SiC layer, the second SiC region, and the surface of the first SiC region interposed between the SiC layer and the second SiC region, a gate electrode is formed on the gate dielectric, a first electrode is embedded in a trench selectively formed in a part where the first SiC region adjoins the second SiC region, and a second electrode is formed on a back surface of the substrate.

公开(公告)号：EP3227913A4

公开(公告)日：2018-07-25

申请号：EP15849828

申请日：2015-08-14

申请人： BOE TECHNOLOGY GROUP CO LTD ,  CHONGQING BOE OPTOELECTRONICS CO LTD

发明人： WANG WU ,  QIU HAIJUN ,  SHANG FEI ,  WANG GUOLEI

IPC分类号： H01L29/417 ,  H01L21/336 ,  H01L27/12 ,  H01L29/45 ,  H01L29/786

CPC分类号： H01L27/1288 ,  H01L21/0274 ,  H01L21/441 ,  H01L21/47573 ,  H01L21/47635 ,  H01L27/1225 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78615 ,  H01L29/78618 ,  H01L29/7869

摘要： Various embodiments provide a thin film transistor (TFT) device, a manufacturing method of the TFT device, and a display apparatus including the TFT device. An etch stop layer (ESL) material is formed on an active layer on a substrate. An electrical conductive layer material is formed on the ESL material for forming a source electrode and a drain electrode. The electrical conductive layer material is patterned to form a first portion of the source electrode containing a first via-hole through the source electrode, and to form a first portion of the drain electrode containing a second via-hole through the drain electrode. The ESL material is patterned to form an etch stop layer (ESL) pattern including a first ESL via-hole connecting to the first via-hole through the source electrode and including a second ESL via-hole connecting to the second via-hole through the drain electrode.

公开(公告)号：EP1970945B1

公开(公告)日：2018-05-09

申请号：EP08152760.8

申请日：2008-03-14

申请人： Nissan Motor Co., Ltd.

发明人： TANIMOTO, Satoshi

IPC分类号： H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/94 ,  H01L29/739

CPC分类号： H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/94

摘要： A MOS type SiC semiconductor device having high reliability and a longer lifespan against TDDB of a gate oxide film is disclosed. The semiconductor device includes a MOS (metal-oxide-semiconductor) structure having a silicon carbide (SiC) substrate, a polycrystalline Si gate electrode, a gate oxide film interposed between the SiC substrate and the polycrystalline Si gate electrode and formed by thermally oxidizing a surface of the SiC substrate, and an ohmic contact electrically contacted with the SiC substrate. The semiconductor device further includes a polycrystalline Si thermally-oxidized film formed by oxidizing a surface of the polycrystalline Si gate electrode. The gate oxide film has a thickness of 20 nm or less, advantageously 15 nm or less.

公开(公告)号：EP3314635A1

公开(公告)日：2018-05-02

申请号：EP15897299.2

申请日：2015-06-27

申请人： INTEL Corporation

发明人： CHU-KUNG, Benjamin ,  LE, Van H. ,  RIOS, Rafael ,  DEWEY, Gilbert ,  CLENDENNING, Scott B. ,  KAVALIEROS, Jack T.

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/45 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76802 ,  H01L21/76883 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66568 ,  H01L29/78

摘要： An apparatus including an integrated circuit device including at least one low density of state metal/semiconductor material interface, wherein the at least one low density of state metal is quantized. An apparatus including an integrated circuit device including at least one interface of a low density of state metal and a semiconductor material, wherein a contact area of the metal at the interface is graded. A method including confining a contact area of a semiconductor material; and forming a metal contact in the contact area.

公开(公告)号：EP3179518A4

公开(公告)日：2018-03-28

申请号：EP16822102

申请日：2016-02-03

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： HUANG YONGCHAO

IPC分类号： H01L29/45 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/04 ,  H01L27/12 ,  H01L27/32 ,  H01L29/16 ,  H01L29/167 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L51/52

CPC分类号： H01L29/4908 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2202/10 ,  H01L21/02527 ,  H01L21/0259 ,  H01L21/0262 ,  H01L21/043 ,  H01L21/044 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/1606 ,  H01L29/167 ,  H01L29/408 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/458 ,  H01L29/66045 ,  H01L29/78606 ,  H01L29/78684 ,  H01L51/5206

摘要： The present disclosure provides a thin film transistor, a method for producing the same, an array substrate and a display apparatus. An electrode of the thin film transistor is made of Cu or Cu alloy, and an anti-oxidization layer is used to prevent oxidization of Cu. The thin film transistor includes a gate electrode, a gate insulation layer, a semiconductor active layer, a source electrode and a drain electrode provided on a base substrate, wherein the gate electrode and/or the drain and source electrodes is/are made of Cu or Cu alloy. The thin film transistor further includes an anti-oxidization layer made of a topological insulator material, the anti-oxidization layer being provided above and in contact with the gate electrode and/or the source and drain electrodes made of Cu or Cu alloy.

公开(公告)号：EP3128553A4

公开(公告)日：2018-01-24

申请号：EP14861185

申请日：2014-07-11

申请人： BOE TECHNOLOGY GROUP CO LTD

发明人： CHOI SEUNGJIN ,  KIM HEECHEOL ,  SONG YOUNGSUK ,  YOO SEONGYEOL

IPC分类号： G02F1/1362 ,  G02F1/1343 ,  H01L27/12

CPC分类号： G02F1/134309 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/134372 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/45

摘要： The embodiments of the invention disclose an array substrate, a manufacturing method thereof and a display device. Due to the fact that the surfaces of a source electrode, a drain electrode and a data line which are arranged on the same layer are provided with an oxide film which is formed after annealing treatment is conducted on the source electrode, the drain electrode and the data line, in the process that the pattern of a pixel electrode is formed on the source electrode, the drain electrode and the data line by the adoption of a composition technology, the oxide film can protect the source electrode and the data line under the oxide film from being corroded by an etching agent when the pattern of the pixel electrode is formed by etching, and the display quality of a display panel will not be affected; meanwhile, a connecting portion enables the drain electrode to be electrically connected with the pixel electrode through a first via hole arranged over the drain electrode and penetrating through the oxide film, therefore the normal display function of the display panel can be ensured.

公开(公告)号：EP3121840A4

公开(公告)日：2017-11-22

申请号：EP15882903

申请日：2015-10-09

申请人： BOE TECHNOLOGY GROUP CO LTD ,  UNIV SOUTH CHINA TECH

发明人： YUAN GUANGCAI ,  YAN LIANGCHEN ,  XU XIAOGUANG ,  WANG LEI ,  PENG JUNBIAO ,  LAN LINFENG

IPC分类号： H01L29/786 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/34 ,  H01L27/12 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L27/1288 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/34 ,  H01L27/1248 ,  H01L29/1079 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

摘要： This invention discloses a thin film transistor and the preparation method thereof, an array substrate, and a display panel, so as to solve the problem that the active layer is prone to be corroded when a metal oxide thin film transistor is produced by a back channel etching process. The preparation method comprises: forming a gate electrode metal thin film on a base substrate, and allowing the gate electrode metal thin film to form a gate electrode metal layer comprising a gate electrode by a patterning process; forming a gate electrode insulating layer on the gate electrode metal layer; forming an active layer on the gate electrode insulating layer; preparing a metal nanoparticle layer on the active layer, said metal nanoparticle layer being used as an etching protection layer; forming a source and drain electrode metal thin film on the base substrate on which the above processes are finished, and allowing the source and drain electrode metal thin film to form a source and drain electrode metal layer comprising a source electrode and a drain electrode by a patterning process, wherein the source electrode and the drain electrode cover a part of the metal nanoparticle layer; removing or oxidizing the part of the metal nanoparticle layer which is not covered by the source electrode and the drain electrode in an oxygen-containing atmosphere; and forming a passivation layer on the source and drain electrode metal layer.

公开(公告)号：EP3243220A1

公开(公告)日：2017-11-15

申请号：EP15819943.0

申请日：2015-12-08

申请人： Silicon Storage Technology Inc.

发明人： CHEN, Chun-ming ,  WU, Man-tang ,  YANG, Jeng-wei ,  SU, Chien-sheng

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.