公开(公告)号：EP3208846B1

公开(公告)日：2018-09-12

申请号：EP17156454.5

申请日：2003-07-24

申请人： Socionext Inc.

发明人： Watanabe, Kenichi

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

摘要： The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

公开(公告)号：EP3361503A1

公开(公告)日：2018-08-15

申请号：EP17206886.8

申请日：2017-12-13

申请人： Renesas Electronics Corporation

发明人： Toshifumi, SUGANAGA

IPC分类号： H01L23/522

CPC分类号： H01L21/76804 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/535 ,  H01L2224/05

摘要： An object of the present invention is to improve the operating characteristics of a semiconductor device.
A semiconductor device has a contact plug that is formed over a semiconductor substrate, a metal wiring that is coupled to the upper surface of the contact plug, and a slit that is formed in the metal wiring. Further, the contact plug is formed at an end of the metal wiring, and the slit is formed at a position apart from the contact plug in an X direction in a planar view. A distance between an edge of the upper surface at the end of the metal wiring and the upper surface of the slit in the X direction is equal to or larger than and twice or smaller than a first plug diameter of the upper surface of the contact plug in the X direction.

公开(公告)号：EP3096350A1

公开(公告)日：2016-11-23

申请号：EP16166762.1

申请日：2016-04-24

申请人： MediaTek Inc.

发明人： LIN, Tzu-Hung ,  HSIAO, Ching-Wen ,  PENG, I-Hsuan

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L25/10 ,  H01L23/538 ,  H01L23/31

CPC分类号： H01L25/16 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/80 ,  H01L24/89 ,  H01L24/92 ,  H01L24/96 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/02317 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/73259 ,  H01L2224/80003 ,  H01L2224/80006 ,  H01L2224/802 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/37001 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/80001

摘要： A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

摘要翻译： 提供半导体封装组件。 该半导体封装组件包括第一半导体封装。 第一半导体封装包括第一半导体管芯。 第一重新分布层（RDL）结构耦合到第一半导体管芯且包括第一导电迹线。 半导体封装组件还包括结合到第一半导体封装的第二半导体封装。 第二半导体封装包括第二半导体管芯。 第二半导体管芯的有源表面面向第一半导体管芯的有源表面。 第二RDL结构耦合到第二半导体管芯且包括第二导电迹线。 第一导电迹线与第二导电迹线直接接触。

公开(公告)号：EP2779244A3

公开(公告)日：2016-10-05

申请号：EP14158995.2

申请日：2014-03-11

申请人： Semiconductor Components Industries, LLC

发明人： Salih, Ali ,  Liu, Chun-Li ,  Grivna, Gordon

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/66 ,  H01L23/532 ,  H01L23/498 ,  H01L23/482 ,  H01L23/522 ,  H01L29/20 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L23/5226 ,  H01L21/6836 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/4824 ,  H01L23/49827 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/84 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2221/68327 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/04034 ,  H01L2224/05111 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/37012 ,  H01L2224/37013 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/3716 ,  H01L2224/37187 ,  H01L2224/3719 ,  H01L2224/37639 ,  H01L2224/37644 ,  H01L2224/37647 ,  H01L2224/37655 ,  H01L2224/37664 ,  H01L2224/40499 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/84801 ,  H01L2224/84815 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13063 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/07811 ,  H01L2224/45099

摘要： In one embodiment, a method of forming a HEMT device may include plating a conductor or a plurality of conductors onto an insulator that overlies a plurality of current carrying electrodes of the HEMT device. The method may also include attaching a connector onto the conductor or attaching a plurality of connectors onto the plurality of conductors.

公开(公告)号：EP3050080A1

公开(公告)日：2016-08-03

申请号：EP14847829.0

申请日：2014-09-25

申请人： Intel Corporation

发明人： CLARKE, James S. ,  SCHMITZ, Anthony C. ,  SCHENKER, Richard E.

IPC分类号： H01L21/28 ,  H01L21/60

CPC分类号： H01L23/481 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit and a method of forming an integrated circuit including a first dielectric layer including a surface, a plurality of first trenches defined in the dielectric layer surface, and a plurality of first wires, wherein each of the first wires are formed in each of the first trenches. The integrated circuit also includes a plurality of second trenches defined in the dielectric layer surface, and a plurality of second wires, wherein each of the second wires are formed in each of the second trenches. Further, the first wires comprise a first material having a first bulk resistivity and the second wires comprise a second material having a second bulk resistivity, wherein the first bulk resistivity and the second bulk resistivity are different.

公开(公告)号：EP2358926A2

公开(公告)日：2011-08-24

申请号：EP09760054.8

申请日：2009-11-19

申请人： Enthone, Inc.

发明人： PANECCASIO, Vincent ,  LIN, Xuan ,  HURTUBISE, Richard ,  CHEN, Qingyun

IPC分类号： C25D3/38 ,  C25D7/12 ,  H01L21/288

CPC分类号： H01L21/76879 ,  C25D3/38 ,  C25D5/02 ,  C25D7/12 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76877 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for metallizing a via feature in a semiconductor integrated circuit device substrate, wherein the semiconductor integrated circuit device substrate comprises a front surface, a back surface, and the via feature and wherein the via feature comprises an opening in the front surface of the substrate, a sidewall extending from the front surface of the substrate inward, and a bottom. The method comprises contacting the semiconductor integrated circuit device substrate with an electrolytic copper deposition chemistry comprising (a) a source of copper ions and (b) a leveler compound, wherein the leveler compound is a reaction product of a dipyridyl compound and an alkylating agent; and supplying electrical current to the electrolytic deposition chemistry to deposit copper metal onto the bottom and sidewall of the via feature, thereby yielding a copper filled via feature.

摘要翻译： 一种用于金属化半导体集成电路器件基板中的通孔特征的方法，其中所述半导体集成电路器件基板包括前表面，后表面和通孔特征，并且其中所述通孔特征包括在所述基板的前表面中的开口 ，从基板的前表面向内延伸的侧壁和底部。 该方法包括使半导体集成电路器件衬底与包含（a）铜离子源和（b）矫光剂化合物的电解铜沉积化学物质接触，其中矫光剂化合物是二吡啶基化合物和烷化剂的反应产物; 并向电解沉积化学物质提供电流以将铜金属沉积到通孔特征的底部和侧壁上，从而产生铜填充的通孔特征。

公开(公告)号：EP2356674A2

公开(公告)日：2011-08-17

申请号：EP09832386.8

申请日：2009-12-01

申请人： Intel Corporation

发明人： O'BRIEN, Kevin, P. ,  AKOLKAR, Rohan, N. ,  INDUKURI, Tejaswi ,  FAJARDO, Arnel M.

IPC分类号： H01L21/28 ,  H01L21/3205

CPC分类号： H01L21/76879 ,  H01L21/288 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

公开(公告)号：EP1077486B1

公开(公告)日：2011-08-03

申请号：EP99918319.7

申请日：1999-05-06

申请人： TOKYO ELECTRON LIMITED

发明人： AKAHORI, Takashi

IPC分类号： H01L21/768 ,  H01L21/314 ,  H01L23/532

CPC分类号： H01L21/0212 ,  H01L21/02274 ,  H01L21/312 ,  H01L21/3127 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： Insulating films 21 through 24 of CF films (fluorine-contained carbon films) are formed on a substrate (not shown). In addition, Cu wiring layers 25 and 26 are formed on the CF films 21 and 23 via an adhesion layer 29 which comprises a Ti layer and a TiC layer. By forming the insulating films 21 through 24 of CF films, Cu in the wiring layers is prevented from diffusing into the insulating films 21 through 24. The relative dielectric constant of the CF film is smaller than the relative dielectric constant of a BCB film.

公开(公告)号：EP1751799B1

公开(公告)日：2011-04-27

申请号：EP05756194.6

申请日：2005-06-02

申请人： Eastman Kodak Company

发明人： TAN, Liang ,  ERHARDT, Herbert, James

IPC分类号： H01L23/58 ,  H01L23/485

CPC分类号： H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/14636 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate; a sealing element spanning a periphery of the substrate that forms a protective boundary for the substrate; a plurality of copper lines spanning the substrate in at least two distinct layers contained within the protective boundary; a first conducting element disposed outside the sealing element; and one or more second conducting elements connecting at least two of the copper lines and that spans the sealing element; wherein the conducting elements are substantially non-oxidizing metals that are resistant to oxidization and that connect the copper line to the first conducting element.

公开(公告)号：EP2003687A1

公开(公告)日：2008-12-17

申请号：EP07739885.7

申请日：2007-03-27

申请人： Tokyo Electron Limited (TEL)

发明人： KIKUCHI, Yoshiyuki

IPC分类号： H01L21/768 ,  H01L21/314 ,  H01L23/522

CPC分类号： H01L21/0217 ,  C23C16/345 ,  C23C16/36 ,  H01L21/0212 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3127 ,  H01L21/3185 ,  H01L21/76811 ,  H01L21/76832 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is a semiconductor device characterized by including a substrate, an insulating film consisting of a fluorine added carbon film formed on the substrate, a barrier layer consisting of a silicon nitride film and a film containing silicon, carbon, and nitride formed on the insulating film, and a hard mask layer having a film containing silicon and oxygen formed on the barrier layer, wherein the barrier layer consists of a silicon nitride film and a film containing silicon, carbon, and nitride that are laminated from the bottom in that order, and functions to prevent the fluorine in the fluorine added carbon film from moving to the hard mask layer.

摘要翻译： 本发明是一种半导体器件，其特征在于，包括：基板，由形成在基板上的氟添加碳膜构成的绝缘膜，由氮化硅膜构成的阻挡层和形成在其上的硅，碳和氮化物的膜 绝缘膜和在阻挡层上形成有含有硅和氧的膜的硬掩模层，其中阻挡层由氮化硅膜和含有硅，碳和氮化物的膜组成，该膜从底部依次层叠 ，并且用于防止氟添加碳膜中的氟移动到硬掩模层。