公开(公告)号：EP3043388A1

公开(公告)日：2016-07-13

申请号：EP15190523.9

申请日：2015-10-20

申请人： Renesas Electronics Corporation

发明人： ABIKO, Yuya ,  EGUCHI, Satoshi ,  ICHIMURA, Akio ,  YAMAGUCHI, Natsuo ,  IIDA, Tetsuya

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/336

CPC分类号： H01L29/0696 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823487 ,  H01L27/0688 ,  H01L29/06 ,  H01L29/0634 ,  H01L29/0684 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66727 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7811

摘要： In a semiconductor device including a super junction structure that p-type columns and n-type columns are periodically arranged, a depth of a p-type column region in a cell region that a semiconductor element is formed is made shallower than a depth of a p-type column region in an intermediate region which surrounds the cell region. Thereby, a breakdown voltage of the cell region becomes lower than a breakdown voltage of the intermediate region. An avalanche breakdown phenomenon is caused to occur preferentially in the cell region in which even when an avalanche current is generated, the current is dispersed and smoothly flows. Thereby, it is possible to avoid local current constriction and breakage incidental thereto and consequently it becomes possible to improve avalanche resistance (an avalanche current amount with which a semiconductor device comes to be broken).

摘要翻译： 在具备周期性地配置有p型柱和n型柱的超结结构的半导体装置中，使形成有半导体元件的单元区域中的p型柱区域的深度比 围绕单元区域的中间区域中的p型柱区域。 由此，单元区域的击穿电压变得低于中间区域的击穿电压。 在产生雪崩电流的电池区域中，优先发生雪崩击穿现象，电流分散并平稳地流动。 由此，可以避免局部电流收缩和附带的破损，并且因此可以改善雪崩电阻（半导体器件被破坏的雪崩电流量）。

公开(公告)号：EP3382760A1

公开(公告)日：2018-10-03

申请号：EP18165147.2

申请日：2018-03-29

申请人： Renesas Electronics Corporation

发明人： ABIKO, Yuya ,  YAMAGUCHI, Natsuo ,  EGUCHI, Satoshi

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L29/1095 ,  H01L21/02529 ,  H01L21/26586 ,  H01L21/308 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/404 ,  H01L29/66053 ,  H01L29/66068 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7813

摘要： In a vertical power MOSFET having a superjunction structure, the withstand voltage of the power MOSFET can be ensured even if the aspect ratios of an n-type column region and a p-type column region are increased so as to vary the impurity concentration of the p-type column region. P-type semiconductor regions PR1 are formed on the sides of an n-type column NC1 adjacent to a p-type column region PC1. In this configuration, the p-type semiconductor region PR1 is formed from the upper end of the n-type column region NC1 to about a half depth of a height from the upper end to the lower end of the side of the n-type column region NC1. This inclines the sides of the overall p-type column region including the p-type semiconductor regions PR1 and the p-type column region PC1.

公开(公告)号：EP3293769A1

公开(公告)日：2018-03-14

申请号：EP17181817.2

申请日：2017-07-18

申请人： Renesas Electronics Corporation

发明人： ABIKO, Yuya ,  EGUCHI, Satoshi ,  SAITO, Shigeaki ,  TANIGUCHI, Daisuke ,  YAMAGUCHI, Natsuo

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L21/225

CPC分类号： H01L29/7802 ,  H01L21/2205 ,  H01L21/2251 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/8611

摘要： Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

摘要翻译： 半导体器件的性能得到改善。 具有其中周期性排列p型列区和n型列区的超结结构的半导体器件如下配置。 每个n型列区具有垂直部分，该垂直部分包括位于沟槽之间的n型外延层和设置在沟槽的侧面上的锥形嵌入式n型外延膜。 每个p型列区域包括设置在沟槽内的嵌入式p型外延膜。 由此，在配置有p型柱区域的沟槽的侧壁上设置锥状的埋入型n型外延膜，因此能够使p型柱区域成为倒梯形状， 对于p型柱状区域中的p型杂质的浓度变化而言为余量。 通过n型杂质（例如As）的横向扩散可以降低导通电阻。