公开(公告)号：EP1246258A4

公开(公告)日：2007-07-18

申请号：EP00986014

申请日：2000-12-28

申请人： SHARP KK

发明人： IWATA HIROSHI ,  SHIBATA AKIHIDE ,  KAKIMOTO SEIZO ,  ADACHI KOUICHIRO ,  NAKANO MASAYUKI

IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device (1910) comprises a semiconductor substrate (100) including an isolation region (101) and an active region (102); a gate electrode (104) formed on gate oxide film (103) over the active area (102) and including side walls covered at least in part by insulating film (105) of the gate electrode side wall; and a source region (106) and a drain region (106) provided across the gate electrode (104) with the insulating film (105) of the gate electrode side wall in between. At least any of the source region (106) and the drain region (106) includes a second face for engagement with contact wiring. The second face makes some angle with the first face (AA') and an angle of less than 80 degrees with the surface of the isolation region.

公开(公告)号：EP1650793A1

公开(公告)日：2006-04-26

申请号：EP05022316.3

申请日：2005-10-13

申请人： ATMEL Germany GmbH

发明人： Bromberger, Christoph, Dipl.-Phys.

IPC分类号： H01L21/74 ,  H01L21/225 ,  H01L21/265

CPC分类号： H01L21/74 ,  H01L21/2251 ,  H01L21/265

摘要： Verfahren zur Herstellung eines Halbleitergegenstandes, indem

eine Silizidschicht (2) aufgebracht wird,
in die Silizidschicht (2) ein Fremdstoff eingebracht wird, der in einem Halbleitergebiet (3) als Dotand wirkt,
die Silizidschicht (2) zumindest teilweise unterhalb des, an die Silizidschicht angrenzenden, monokristallinen Halbleitergebietes (3) angeordnet wird, so dass die Silizidschicht (2) unter einer Schicht aus dem monokristallinen Halbleitergebiet (3) zumindest teilweise vergraben wird,
und
mittels eines späteren Hochtemperaturschrittes der als Dotand wirkende Fremdstoff zumindest teilweise in das angrenzende monokristalline Halbleitergebiet (3) aus der zumindest teilweise vergrabenen Silizidschicht (2) eindiffundiert wird.

摘要翻译： 该方法包括将在半导体区域（3）中充当掺杂剂的杂质引入到硅化物层（2）中。 该层部分地位于与该层相邻的单晶半导体区域的下方，使得该层部分地埋在该半导体区域的一层之下。 杂质从部分埋置的硅化物层部分地扩散到相邻的半导体区域中。 独立权利要求还包括以下内容：（A）具有掩埋硅化物层的半导体产品（B）应用半导体产品制造方法（C）具有发射极半导体区域（D）的高频双极晶体管 应用硅化物层。

公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

申请人： IBM

发明人： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC分类号： H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC分类号： H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

摘要： A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

摘要翻译： 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP2206154B1

公开(公告)日：2011-06-29

申请号：EP08843598.7

申请日：2008-10-22

申请人： NXP B.V.

发明人： PEAKE, Steven, Thomas ,  RUTTER, Philip ,  ROGERS, Christopher ,  DROBNIS, Miron ,  BUTLER, Andrew

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L21/336 ,  H01L21/265 ,  H01L21/225

CPC分类号： H01L29/7813 ,  H01L21/2251 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

公开(公告)号：EP1806778B1

公开(公告)日：2011-02-09

申请号：EP05793133.9

申请日：2005-10-12

申请人： Shin-Etsu Handotai Co., Ltd.

发明人： NAGOYA, Takatoshi, c/o Isobe R&D Center Shin-Etsu Handotai Co. Ltd.

IPC分类号： H01L21/324 ,  H01L21/22 ,  H01L21/225

CPC分类号： H01L21/67757 ,  H01L21/2251 ,  H01L21/324

摘要： In an annealed wafer manufacturing method, a boat whereupon semiconductor wafers are placed is inserted into a furnace core pipe, while introducing an inert gas into the furnace, and after all the semiconductor wafers to be products reach a soaking part, the inserting speed of the boat whereupon the semiconductor wafers are placed is reduced and/or temporarily stopped to maintain a space between the furnace core pipe and a shutter for a prescribed time, then, the furnace core pipe is closed by the shutter. Thus, change of specific resistivity of the wafer before and after heat treatment due to wafer contamination by conductive impurities during heat treatment is more surely prevented.

公开(公告)号：EP1246258A1

公开(公告)日：2002-10-02

申请号：EP00986014.9

申请日：2000-12-28

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  SHIBATA, Akihide ,  KAKIMOTO, Seizo ,  ADACHI, Kouichiro ,  NAKANO, Masayuki LM Narayasuraginomichi 201

IPC分类号： H01L29/78

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device 1910 comprises a semiconductor substrate 100 including an isolation region 101 and an active region 102, a gate electrode 104 provided on the active region 102 via a gate insulating film 103 , part of a side of the gate electrode 104 being covered with a gate electrode side wall insulating film 105 , and a source region 106 and a drain region 106 provided on opposite sides of the gate electrode 104 via the gate electrode side wall insulating film 105 . At least one of the source region 106 and the drain region 106 has a second surface for contacting a contact conductor. The second surface is tilted with respect to a first surface A-A' . An angle between the second surface and a surface of the isolation region is 80 degrees or less.

摘要翻译： 半导体器件1910包括半导体衬底100，其包括隔离区域101和有源区域102，经由栅极绝缘膜103设置在有源区域102上的栅电极104，栅电极104的一侧的一部分被覆盖有 栅电极侧壁绝缘膜105，以及经由栅电极侧壁绝缘膜105设置在栅极电极104的相对侧上的源极区域106和漏极区域106.源极区域106和漏极区域106中的至少一个 具有用于接触接触导体的第二表面。 第二表面相对于第一表面A-A'倾斜。 第二表面与隔离区域的表面之间的角度为80度以下。

公开(公告)号：EP1246258B1

公开(公告)日：2011-02-23

申请号：EP00986014.9

申请日：2000-12-28

申请人： Sharp Kabushiki Kaisha

发明人： IWATA, Hiroshi ,  SHIBATA, Akihide ,  KAKIMOTO, Seizo ,  ADACHI, Kouichiro ,  NAKANO, Masayuki LM Narayasuraginomichi 201

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/225

CPC分类号： H01L29/66628 ,  H01L21/2251 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7834 ,  H01L29/78657

摘要： A semiconductor device (1910) comprises a semiconductor substrate (100) including an isolation region (101) and an active region (102); a gate electrode (104) formed on gate oxide film (103) over the active area (102) and including side walls covered at least in part by insulating film (105) of the gate electrode side wall; and a source region (106) and a drain region (106) provided across the gate electrode (104) with the insulating film (105) of the gate electrode side wall in between. At least any of the source region (106) and the drain region (106) includes a second face for engagement with contact wiring. The second face makes some angle with the first face (AA') and an angle of less than 80 degrees with the surface of the isolation region.

公开(公告)号：EP2206154A1

公开(公告)日：2010-07-14

申请号：EP08843598.7

申请日：2008-10-22

申请人： NXP B.V.

发明人： PEAKE, Steven, Thomas ,  RUTTER, Philip ,  ROGERS, Christopher ,  DROBNIS, Miron ,  BUTLER, Andrew

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/336 ,  H01L29/423 ,  H01L21/265 ,  H01L21/225

CPC分类号： H01L29/7813 ,  H01L21/2251 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734

摘要： A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

公开(公告)号：EP1605518A3

公开(公告)日：2006-09-06

申请号：EP05012020.3

申请日：2005-06-03

申请人： LG Electronics, Inc.

发明人： Kim, Geun Ho ,  Lee, Seung Yeob, No. 402, Jeongseokgreenbilla

IPC分类号： H01L29/866 ,  H01L21/329 ,  H01L21/225

CPC分类号： H01L29/66106 ,  H01L21/2251 ,  H01L29/866

摘要： The present invention is directed to a Zener diode and a method for fabricating the same. According to the present invention, a voltage regulator device can be fabricated by carrying out a diffusion process without using a diffusion mask. Further, a PNP (or NPN) Zener diode having a bi-directional threshold voltage characteristic or a PN Zener diode can be fabricated without any photolithographic process or using the minimum number of processes. Therefore, the number of processing steps can be reduced and the yield thereof can be increased.

公开(公告)号：EP3293769A1

公开(公告)日：2018-03-14

申请号：EP17181817.2

申请日：2017-07-18

申请人： Renesas Electronics Corporation

发明人： ABIKO, Yuya ,  EGUCHI, Satoshi ,  SAITO, Shigeaki ,  TANIGUCHI, Daisuke ,  YAMAGUCHI, Natsuo

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L21/225

CPC分类号： H01L29/7802 ,  H01L21/2205 ,  H01L21/2251 ,  H01L21/2253 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/66712 ,  H01L29/7811 ,  H01L29/8611

摘要： Properties of a semiconductor device are improved. A semiconductor device having a superjunction structure, in which p-type column regions and n-type column regions are periodically arranged, is configured as follows. Each n-type column region has a vertical section including an n-type epitaxial layer located between trenches and a tapered embedded n-type epitaxial film disposed on a side face of the trench. Each p-type column region includes an embedded p-type epitaxial film disposed within the trench. The tapered embedded n-type epitaxial film is thus provided on the sidewall of the trench in which the p-type column region is to be disposed, thereby the p-type column region is allowed to have an inverted trapezoidal shape, leading to an increase in margin for a variation in concentration of a p-type impurity in the p-type column region. On resistance can be reduced by lateral diffusion of an n-type impurity (for example, As).

摘要翻译： 半导体器件的性能得到改善。 具有其中周期性排列p型列区和n型列区的超结结构的半导体器件如下配置。 每个n型列区具有垂直部分，该垂直部分包括位于沟槽之间的n型外延层和设置在沟槽的侧面上的锥形嵌入式n型外延膜。 每个p型列区域包括设置在沟槽内的嵌入式p型外延膜。 由此，在配置有p型柱区域的沟槽的侧壁上设置锥状的埋入型n型外延膜，因此能够使p型柱区域成为倒梯形状， 对于p型柱状区域中的p型杂质的浓度变化而言为余量。 通过n型杂质（例如As）的横向扩散可以降低导通电阻。