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    AN INSULATED-GATE BIPOLAR TRANSISTOR DEVICE AS WELL AS A DATA TRANSMISSION SYSTEM IMPLEMENTING SUCH INSULATED-GATE BIPOLAR TRANSISTOR DEVICE
    1.
    发明公开
    AN INSULATED-GATE BIPOLAR TRANSISTOR DEVICE AS WELL AS A DATA TRANSMISSION SYSTEM IMPLEMENTING SUCH INSULATED-GATE BIPOLAR TRANSISTOR DEVICE 审中-公开

    公开(公告)号：EP4407681A1

    公开(公告)日：2024-07-31

    申请号：EP23153397.7

    申请日：2023-01-26

    申请人： Nexperia B.V.

    发明人： Holland, Steffen

    IPC分类号： H01L27/02 ,  H01L29/739

    CPC分类号： H01L27/0259 ,  H01L27/0262 ,  H01L29/7393 ,  H01L29/7404 ,  H01L29/083 ,  H01L29/0692

    摘要： An insulated-gate bipolar transistor device comprising:
    a first region doped with a first type of charge carriers;
    a second region doped with a second type of charge carriers different from the first type of charge carriers;
    a third region doped with the first type of charge carriers;
    a fourth region doped with the second type of charge carriers;
    a first, emitter terminal electrically connected with the first region and a second, collector terminal electrically connected with the third region and the fourth region; and
    a gate structure disposed on the third region with one end adjacent to the second region and with another end adjacent the fourth region; as well as
    a diode structure having a first diode structure terminal electrically connected with the collector terminal and a second diode structure terminal electrically connected with the gate terminal of the gate structure.

    LATERAL INSULATED-GATE BIPOLAR TRANSISTOR
    2.
    发明公开
    LATERAL INSULATED-GATE BIPOLAR TRANSISTOR 审中-公开
    横向绝缘栅双极型晶体管

    公开(公告)号：EP3240039A1

    公开(公告)日：2017-11-01

    申请号：EP15871728.0

    申请日：2015-09-10

    申请人： CSMC Technologies Fab1 Co., Ltd.

    发明人： QI, Shukun

    IPC分类号： H01L29/739 ,  H01L29/06

    CPC分类号： H01L29/7394 ,  H01L29/0834 ,  H01L29/7393

    摘要： A lateral insulated gate bipolar transistor comprises a substrate (10); an anode terminal located on the substrate, comprising: an N-type buffer region (51) located on the substrate (10); a P well (53) located in the N-type buffer region; an N-region (55) located in the P well (53); two P+ shallow junctions (57) located on a surface of the P well (53); and an N+ shallow junction (59) located between the two P+ shallow junctions (57); a cathode terminal located on the substrate; a draft region (30) between the anode terminal and cathode terminal; and a gate (62) between the anode terminal and cathode terminal.

    摘要翻译： 横向绝缘栅双极型晶体管包括衬底（10）; 位于所述基板上的阳极端子，所述阳极端子包括：位于所述基板上的N型缓冲区域; 位于N型缓冲区中的P阱（53） 位于P阱（53）中的N区（55）; 位于P阱（53）表面上的两个P +浅结（57）; 和位于两个P +浅结（57）之间的N +浅结（59）; 位于基板上的阴极端子; 阳极端子和阴极端子之间的通风区域（30） 和在阳极端子和阴极端子之间的栅极（62）。

    COOLING OF WIDE BANDGAP SEMICONDUCTOR DEVICES
    3.
    发明公开
    COOLING OF WIDE BANDGAP SEMICONDUCTOR DEVICES 审中-公开
    宽带半导体器件的冷却

    公开(公告)号：EP3232470A1

    公开(公告)日：2017-10-18

    申请号：EP16165167.4

    申请日：2016-04-13

    申请人： ABB Schweiz AG

    发明人： Agostini, Bruno ,  Torresin, Daniele ,  Agostini, Francesco ,  Habert, Mathieu ,  Rahimo, Munaf

    IPC分类号： H01L23/427 ,  H01L23/473 ,  F25B25/00 ,  H01L29/16 ,  H01L29/20 ,  H01L29/22

    CPC分类号： H01L23/427 ,  F25B25/005 ,  H01L23/473 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/7393 ,  H01L29/78 ,  H05K7/20936

    摘要： A power device (10) comprises at least one power semiconductor module (12) comprising a wide bandgap semiconductor element (18); and a cooling system (16) for actively cooling the wide bandgap semiconductor element (18) with a cooling medium, wherein the cooling system (16) comprises a refrigeration device (40) for lowering a temperature of the cooling medium below an ambient temperature of the power device (10); wherein the cooling system (16) is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor (18) element is below 100° C.

    摘要翻译： 功率器件（10）包括至少一个功率半导体模块（12），该功率半导体模块（12）包括宽带隙半导体元件（18）; 以及用冷却介质主动冷却宽带隙半导体元件（18）的冷却系统（16），其中冷却系统（16）包括用于将冷却介质的温度降低至低于环境温度的制冷设备（40） 该功率装置​​（10）; 其中所述冷却系统（16）适于以这样的方式降低所述冷却介质的温度，使得所述宽带隙半导体（18）元件的温度低于100℃

    VERTICAL DMOS BJT SEMICONDUCTOR DEVICE
    5.
    发明公开
    VERTICAL DMOS BJT SEMICONDUCTOR DEVICE 审中-公开
    VERTIKALES DMOS或BJT HALBLEITERBAUELEMENT

    公开(公告)号：EP3151283A1

    公开(公告)日：2017-04-05

    申请号：EP15187379.1

    申请日：2015-09-29

    申请人： Nexperia B.V.

    发明人： Holland, Steffen ,  Habenicht, Soenke

    IPC分类号： H01L29/417 ,  H01L29/735 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

    CPC分类号： H01L29/7827 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0873 ,  H01L29/0882 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/41741 ,  H01L29/41758 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/735 ,  H01L29/7393 ,  H01L29/7809 ,  H01L29/7816

    摘要： A semiconductor device (300; 500) comprising: a doped semiconductor substrate (302); an epitaxial layer (304; 504), disposed on top of the substrate, the epitaxial layer having a lower concentration of dopant than the substrate; a switching region (310, 312; 510, 512) disposed in the epitaxial layer; and a contact diffusion (350; 550) disposed in the epitaxial layer, the contact diffusion having a higher concentration of dopant than the epitaxial layer; wherein the epitaxial layer forms a barrier between the contact diffusion and the substrate and the switching region comprises a plurality of limbs (510(i), 510(ii)) interdigitated with limbs of the contact diffusion (550(i)).

    摘要翻译： 一种半导体器件（300; 500），包括：掺杂半导体衬底（302）; 外延层（304; 504），设置在所述衬底的顶部上，所述外延层具有比所述衬底更低的掺杂剂浓度; 设置在所述外延层中的开关区域（310,312; 510,512）; 和设置在所述外延层中的接触扩散（350; 550），所述接触扩散具有比所述外延层更高的掺杂剂浓度; 其中所述外延层在所述接触扩散和所述衬底之间形成阻挡层，并且所述开关区域包括与所述接触扩散部分（550（i））的四肢交叉的多个分支（510（i），510（ii））。

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：EP3076425A1

    公开(公告)日：2016-10-05

    申请号：EP13881450.4

    申请日：2013-11-27

    申请人： Renesas Electronics Corporation

    发明人： MORI, Takahiro

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/1083 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/402 ,  H01L29/7393 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7835

    摘要： A semiconductor substrate (SUB) has a recessed portion (CP1) and a recessed portion (CP2) in a main surface. An n + source region (SR) and an n + drain region (DR) sandwich the recessed portion (CP1) and the recessed portion (CP2) in the main surface. A p - epitaxial region (EP) and a p-type well region (WL) serving as a channel formation region are formed in the main surface between the n + source region (SR) and the recessed portion (CP1). A gate electrode layer (GE) is formed on the channel region with a gate insulation film (GI) interposed therebetween, and extends onto an element isolation insulation film (SI) in the recessed portion (CP1). The recessed portion (CP1) and the recessed portion (CP2) are arranged to be adjacent to each other to sandwich a substrate protruding portion (CV) protruding toward the main surface side with respect to a bottom portion of each of the recessed portion (CP1) and the recessed portion (CP2).

    摘要翻译： 半导体衬底（SUB）在主表面中具有凹陷部分（CP1）和凹陷部分（CP2）。 n +源极区（SR）和n +漏极区（DR）在主表面中夹住凹陷部分（CP1）和凹陷部分（CP2）。 在n +源极区（SR）和凹陷部（CP1）之间的主表面中形成用作沟道形成区的p-外延区（EP）和p型阱区（WL）。 栅极电极层（GE）隔着栅极绝缘膜（GI）形成在沟道区域上，并延伸到凹部（CP1）内的元件分离绝缘膜（SI）上。 凹部（CP1）与凹部（CP2）以相对于凹部（CP1）的底部向主面侧突出的基板突出部（CV）彼此相邻的方式配置 ）和凹部（CP2）。

    SILICON CARBIDE DEVICE
    10.
    发明公开
    SILICON CARBIDE DEVICE 审中-公开
    SILICIUMCARBID-BAUTEIL

    公开(公告)号：EP3070734A1

    公开(公告)日：2016-09-21

    申请号：EP16167448.6

    申请日：2012-10-23

    申请人： Anvil Semiconductors Limited

    发明人： WARD, Peter

    IPC分类号： H01L21/02 ,  H01L29/66 ,  H01L29/739 ,  H01L29/74 ,  H01L29/16 ,  H01L29/04

    CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/02645 ,  H01L21/3081 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66363 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74

    摘要： A method comprisesproviding a monocrystalline silicon wafer (11) having a principal surface (17) which supports a masking layer (24), for example silicon dioxide or polycrystalline silicon, having windows (25) to expose corresponding regions of the silicon wafer, forming silicon carbide seed regions (30) on the exposed regions of the wafer, for example by forming carbon and converting the carbon into silicon carbide, and growing monocrystalline silicon carbide (31) on the silicon carbide seed regions. Thus, monocrystalline silicon carbide can be formed selectively on the silicon wafer which can help to avoid wafer bow.

    摘要翻译： 一种方法包括提供具有主表面（17）的单晶硅晶片（11），该主表面（17）支撑掩模层（24），例如二氧化硅或多晶硅，具有窗口（25）以暴露硅晶片的相应区域，形成硅 碳化物种子区域（30），例如通过形成碳并将碳转化为碳化硅，以及在碳化硅种子区域上生长单晶碳化硅（31）。 因此，可以在硅晶片上选择性地形成单晶碳化硅，这有助于避免晶片弓形。