公开(公告)号：EP3343615A3

公开(公告)日：2018-08-22

申请号：EP17203057.9

申请日：2017-11-22

Applicant: Renesas Electronics Corporation

Inventor： Kawashima, Yoshiyuki ,  Hashimoto, Takashi

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/28282 ,  H01L23/528 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.

公开(公告)号：EP3291239A1

公开(公告)日：2018-03-07

申请号：EP17187447.2

申请日：2017-08-23

Applicant: Renesas Electronics Corporation

Inventor： Saito, Tomoya ,  Fujito, Masamichi ,  Ando, Koichi ,  Hashimoto, Takashi

IPC: G11C16/34

CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0793 ,  G06F2212/72 ,  G11C16/28 ,  G11C16/3431 ,  G11C29/50004

Abstract: The present invention aims at providing a flash memory that can perform a refresh operation at an appropriate time before a read error occurs. The controller performs the first read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the first speed, and concurrently, the sense amplifier is made to read data; the second read operation in which the memory cell as the read target is made to draw out the potential of one of the bit lines, the bit line potential controller is made to draw out the potential of the other of the bit lines at the second speed faster than the first speed, and concurrently, the sense amplifier is made to read data; and the refresh operation in which, when the data read by the first read operation and the data read by the second read operation are determined to be different, the data stored in the memory cell as the read target is rewritten.

Abstract translation: 本发明旨在提供一种闪存，其能够在发生读取错误之前的适当时间执行刷新操作。 控制器执行第一读取操作，在该第一读取操作中，使作为读取目标的存储器单元引出一个位线的电位，使位线电势控制器将位线中的另一个的电位引出到 第一速度，同时使读出放大器读取数据; 执行第二读取操作，其中使作为读取目标的存储器单元取出一个位线的电位，使位线电位控制器以第二速度取出另一位线的电位 比第一速度快，同时使读出放大器读取数据; 以及刷新操作，其中当由第一读取操作读取的数据和由第二读取操作读取的数据被确定为不同时，存储在作为读取目标的存储器单元中的数据被重写。

公开(公告)号：EP3343615A2

公开(公告)日：2018-07-04

申请号：EP17203057.9

申请日：2017-11-22

Applicant: Renesas Electronics Corporation

Inventor： Kawashima, Yoshiyuki ,  Hashimoto, Takashi

IPC: H01L27/1157 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/1157 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/28282 ,  H01L23/528 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.