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    PROCESSING APPARATUS AND CONTROL METHOD THEREOF
    3.
    发明公开
    PROCESSING APPARATUS AND CONTROL METHOD THEREOF 审中-公开
    VERARBEITUNGSVORRICHTUNG UND STEUERUNGSVERFAHRENDAFÜR

    公开(公告)号：EP3073378A1

    公开(公告)日：2016-09-28

    申请号：EP16162394.7

    申请日：2016-03-24

    申请人： Renesas Electronics Corporation

    发明人： UEDA, Hiroshi ,  MOCHIZUKI, Seiji ,  KAYA, Toshiyuki ,  IWATA, Kenichi ,  MATSUBARA, Katsushige

    IPC分类号： G06F9/50 ,  H04N19/176

    CPC分类号： G06F13/4068 ,  G06F9/5066 ,  G06F13/28 ,  H04N19/176 ,  H04N19/423 ,  H04N19/436

    摘要： A plurality of transfer modules (402-0 to 402-M) that transfer data between processing units are provided so as to respectively correspond to a plurality of processing units (401-0 to 401-M). First ring buses (403-0 to 403-M) connect, for each of the processing units (401-0 to 401-M), subunits within a corresponding processing unit and the transfer module corresponding to the processing unit so that they form a ring shape. The plurality of transfer modules (402-0 to 402-M) are connected so that they form a ring shape by a second ring bus (404).

    摘要翻译： 提供在处理单元之间传送数据的多个传送模块（402-0至402-M），以分别对应于多个处理单元（401-0至401-M）。 对于每个处理单元（401-0至401-M），第一环形总线（403-0至403-M）连接相应处理单元内的子单元和对应于处理单元的传送模块，从而形成 环形。 多个传送模块（402-0至402-M）被连接成使得它们通过第二环形总线（404）形成环形。

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    4.
    发明公开
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：EP3882774A1

    公开(公告)日：2021-09-22

    申请号：EP21162365.7

    申请日：2021-03-12

    申请人： Renesas Electronics Corporation

    发明人： MATSUBARA, Katsushige ,  HASHIMOTO, Ryoji ,  IRITA, Takahiro ,  SHIMADA, Kenichi ,  SHIBAYAMA, Tetsuya

    IPC分类号： G06F11/10

    摘要： In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    7.
    发明公开
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：EP3477882A1

    公开(公告)日：2019-05-01

    申请号：EP18196131.9

    申请日：2018-09-23

    申请人： Renesas Electronics Corporation

    发明人： MATSUBARA, Katsushige ,  MOCHIZUKI, Seiji ,  MATSUMOTO, Keisuke

    IPC分类号： H04L1/00 ,  H04L29/06 ,  H04N19/503 ,  H04N19/65

    摘要： Provided is a data processing device that reduces the amount of memory access in a case where data and an error control code are to be stored in a memory. The processing device includes a data compression section, a code generation section, a binding section, and a transfer section. The data compression section generates second data by performing a predetermined compression process on first data that is to be stored in a memory and of a predetermined data length. The code generation section generates an error control code for the first data or the second data. The binding section generates third data by binding the second data generated by the data compression section to the error control code generated by the code generation section. The transfer section transfers the third data generated by the binding section to the memory in units of the predetermined data length.

    SEMICONDUCTOR DEVICE AND MEMORY ACCESS METHOD
    8.
    发明公开
    SEMICONDUCTOR DEVICE AND MEMORY ACCESS METHOD 审中-公开

    公开(公告)号：EP3462322A1

    公开(公告)日：2019-04-03

    申请号：EP18193010.8

    申请日：2018-09-06

    申请人： Renesas Electronics Corporation

    发明人： MATSUMOTO, Keisuke ,  MOCHIZUKI, Seiji ,  UEDA, Hiroshi ,  MATSUBARA, Katsushige

    IPC分类号： G06F12/02

    摘要： Regarding association between an area where compressed data is stored and an area where auxiliary information required to access the compressed data is stored, it is necessary to manage the association by software for each processing unit, so that the processing becomes complicated. A management unit memory area including a compressed data storage area and an auxiliary information storage area including auxiliary information are defined on a memory space. By calculating an auxiliary information address from an address indicating a location on a memory where a management unit memory space is set, an address of the auxiliary information storage area, and an address of the compressed data, the compressed data and the auxiliary information are associated with each other and the auxiliary information is read.

    SEMICONDUCTOR DEVICE AND ITS MEMORY ACCESS CONTROL METHOD
    9.
    发明公开
    SEMICONDUCTOR DEVICE AND ITS MEMORY ACCESS CONTROL METHOD 审中-公开
    半导体器件及其存储器访问控制方法

    公开(公告)号：EP3246821A1

    公开(公告)日：2017-11-22

    申请号：EP17168956.5

    申请日：2017-05-02

    申请人： Renesas Electronics Corporation

    发明人： MOCHIZUKI, Seiji ,  MATSUBARA, Katsushige ,  IMAOKA, Ren ,  UEDA, Hiroshi ,  HASHIMOTO, Ryoji ,  KAYA, Toshiyuki

    IPC分类号： G06F12/14 ,  G06F21/79 ,  G06F9/46

    摘要： There is a problem that memory protection against access to a shared memory by a sub-arithmetic unit used by a program executed in a main-arithmetic unit cannot be performed in a related-art semiconductor device. According to one embodiment, a semiconductor device includes a sub-arithmetic unit configured to execute a process of a part of a program executed by a main-arithmetic unit, and a shared memory shared by the main-arithmetic unit and the sub-arithmetic unit, in which the sub-arithmetic unit includes a memory protection unit configured to permit or prohibit access to the shared memory based on an access permission range address value provided from the main-arithmetic unit, the access to the shared memory being access that arises from a process executed by the sub-arithmetic unit.

    摘要翻译： 在现有技术的半导体装置中，存在无法在由主运算装置执行的程序中使用的子运算装置访问共用存储器的存储器保护的问题。 根据一个实施例，一种半导体装置包括：子运算单元，被配置为执行由主运算单元执行的程序的一部分的处理;以及由主运算单元和子运算单元共享的共享存储器 其中，所述子算术单元包括存储器保护单元，所述存储器保护单元被配置为基于从所述主运算单元提供的访问许可范围地址值来允许或禁止访问所述共享存储器，所述对共享存储器的访问是由 由子运算单元执行的处理。

    SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND CONTROL METHOD OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和半导体器件的控制方法

    公开(公告)号：EP3176702A1

    公开(公告)日：2017-06-07

    申请号：EP16194438.4

    申请日：2016-10-18

    申请人： Renesas Electronics Corporation

    发明人： HASE, Masaru ,  TSUDA, Tetsuji ,  NISHIKAWA, Naohiro ,  INOUE, Yuki ,  MOCHIZUKI, Seiji ,  MATSUBARA, Katsushige ,  IMAOKA, Ren

    IPC分类号： G06F15/173 ,  G06F13/362 ,  G06F15/78

    CPC分类号： G06F13/362 ,  G06F13/4022 ,  G06F15/17312 ,  G06F15/7807

    摘要： In a semiconductor device, a load of CPU required for arbitration when using a shared resource is reduced.
    The semiconductor device includes a CPU section and a hardware IP. In the CPU section, software modules are executed. The hardware IP includes a storage unit, an arbitration unit, and a calculation unit. The storage unit includes control receiving units that receive operation requests transmitted by the software modules, respectively. The calculation unit performs processing based on an operation request transmitted from the control receiving units. The arbitration unit controls information transmission between the control receiving units and the calculation unit so that the calculation unit receives only an operation request from any one of the control receiving units.

    摘要翻译： 在半导体装置中，使用共享资源时仲裁所需的CPU的负载减少。 该半导体器件包括CPU部分和硬件IP。 在CPU部分，执行软件模块。 硬件IP包括存储单元，仲裁单元和计算单元。 存储单元包括分别接收由软件模块发送的操作请求的控制接收单元。 计算单元基于从控制接收单元发送的操作请求来执行处理。 仲裁单元控制控制接收单元和计算单元之间的信息传输，使得计算单元仅接收来自任何一个控制接收单元的操作请求。