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    SEMICONDUCTOR DEVICE AND PROCESSING METHOD USING THE SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE AND PROCESSING METHOD USING THE SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP3579112A2

    公开(公告)日：2019-12-11

    申请号：EP19176102.2

    申请日：2019-05-23

    申请人： Renesas Electronics Corporation

    发明人： HASHIMOTO, Ryoji ,  MATSUMOTO, Keisuke ,  VAN HUYNH, Nhat

    IPC分类号： G06F13/00 ,  G06K9/36 ,  G06T1/60

    摘要： The present invention provides a semiconductor device enabling efficient compression without increasing the circuit size and a processing method using the semiconductor device. According to an embodiment, an image processor includes: a coding circuit to perform image processing on a target image divided into a plurality of tiles, the image processing being performed on each of the tiles; a determination circuit to determine whether a tile boundary is included in the area of an image block serving as a unit of compression of the target image; and a compression circuit to compress the image block image-processed by the coding circuit, according to a determination result of the determination circuit.

    DECODING METHOD, DECODING APPARATUS, AND ENCODING METHOD
    5.
    发明公开
    DECODING METHOD, DECODING APPARATUS, AND ENCODING METHOD 审中-公开

    公开(公告)号：EP3709649A1

    公开(公告)日：2020-09-16

    申请号：EP20162355.0

    申请日：2020-03-11

    申请人： Renesas Electronics Corporation

    发明人： HASHIMOTO, Ryoji ,  MOCHIZUKI, Seiji

    IPC分类号： H04N19/176 ,  H04N19/52 ,  H04N19/573

    摘要： The decoding method is a decoding method for decoding a bitstream, in which a difference between a reference index and a prediction value of a motion vector is used for each block obtained by dividing each frame of a moving picture in which a plurality of frames are consecutive, in which a plurality of groups having a predetermined number of blocks are defined in each frame and a limitation is applied for each group to a range of reference index and differences of blocks other than the first block in the group, and the decoding method includes a step for determining whether the block to be decoded is the first block of the group, a step for decoding using the reference index and difference if the block is not the first block, and a step for decoding using the limited reference index and differences if the block is not the first block.

    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD
    8.
    发明公开
    DATA PROCESSING DEVICE AND DATA PROCESSING METHOD 审中-公开

    公开(公告)号：EP3882774A1

    公开(公告)日：2021-09-22

    申请号：EP21162365.7

    申请日：2021-03-12

    申请人： Renesas Electronics Corporation

    发明人： MATSUBARA, Katsushige ,  HASHIMOTO, Ryoji ,  IRITA, Takahiro ,  SHIMADA, Kenichi ,  SHIBAYAMA, Tetsuya

    IPC分类号： G06F11/10

    摘要： In a data processing device comprising a memory controller controlling writing/reading of data to/from the memory, a processor requesting writing/reading of data, and an error detection module requesting writing/reading of data to/from the memory controller in accordance with a request from the processor, an error detection module calculates a first error detection code of the first data having a write request from the processor, reads the second data having a read request from the processor from the memory, calculates a second error detection code from the read data, compares the first error detection code and the second error detection code, and transmits the result of the comparison to the external module.

    DATA PROCESSING DEVICE, DATA PROCESSING SYSTEM AND METHOD THEREFOR
    10.
    发明公开
    DATA PROCESSING DEVICE, DATA PROCESSING SYSTEM AND METHOD THEREFOR 审中-公开
    DATENVERARBEITUNGSVORRICHTUNG，DATENVERARBEITUNGSSYSTEM UND VERFAHRENDAFÜR

    公开(公告)号：EP3091440A1

    公开(公告)日：2016-11-09

    申请号：EP15834785.6

    申请日：2015-03-12

    申请人： Renesas Electronics Corporation

    发明人： SUGIMOTO, Takahiko ,  UNE, Tomohiro ,  UEDA, Hiroshi ,  HASHIMOTO, Ryoji ,  KAYA, Toshiyuki

    IPC分类号： G06F13/00

    CPC分类号： G06F13/4221 ,  G06F13/00 ,  G06F13/4009 ,  G06F13/4027

    摘要： A data selector circuit (2) divides a group of data including a plurality of types of data into the plurality of types of data. A first compression circuit (4a) and a second compression circuit (4b) respectively compress the plurality of types of data in parallel with each other in accordance with each of the plurality of types of data. The first compression circuit (4a) compresses data (b1) and obtains compressed data (b2). The second compression circuit (4b) compresses data (c1) and obtains compressed data (c2). The data transmission circuit (6) transmits the compressed data (b2) and the compressed data (c2) to a terminal.

    摘要翻译： 数据选择器电路（2）将包括多种类型的数据的数据组划分成多种类型的数据。 第一压缩电路（4a）和第二压缩电路（4b）根据多种类型的数据分别彼此并行地压缩多种类型的数据。 第一压缩电路（4a）压缩数据（b1）并获得压缩数据（b2）。 第二压缩电路（4b）压缩数据（c1）并获得压缩数据（c2）。 数据发送电路（6）将压缩数据（b2）和压缩数据（c2）发送到终端。