公开(公告)号：EP2378549A1

公开(公告)日：2011-10-19

申请号：EP11001643.3

申请日：2010-04-06

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Bourdelle, Konstantin ,  Ferrant, Richard ,  Nguyen, Bich-Yen

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular, a semiconductor-on-insulator (SOI) substrate, comprising the steps of a) providing a donor substrate and a handle substrate, b) forming one or more alignment marks in, in particular inside, the handle substrate, and then c) attaching, in particular by bonding, the donor and the handle substrate to obtain a donor-handle compound.

摘要翻译： 本发明涉及一种用于制造半导体衬底，尤其是绝缘体上半导体（SOI）衬底的方法，包括以下步骤：a）提供施主衬底和处理衬底，b）在衬底上形成一个或多个对准标记 ，特别是在处理衬底内部，然后c）特别地通过结合施主和处理衬底以获得施主 - 处理化合物。

公开(公告)号：EP2375442A1

公开(公告)日：2011-10-12

申请号：EP10290181.6

申请日：2010-04-06

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard ,  Bourdelle, Konstantin ,  Nguyen, Bich-Yen

IPC分类号： H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate, comprising the steps of a) providing a donor substrate and a handle substrate, b) forming a pattern of one or more doped regions in, in particular inside, the handle substrate, and then c) attaching, in particular by bonding, the donor and the handle substrate to obtain a donor-handle compound.

摘要翻译： 本发明涉及一种用于制造半导体衬底，尤其是绝缘体上半导体衬底的方法，包括以下步骤：a）提供施主衬底和处理衬底，b）形成一个或多个掺杂区域的图案， 特别是在处理衬底内部，然后c）特别地通过结合施主和处理衬底来获得施主 - 处理化合物。

公开(公告)号：EP2333779A1

公开(公告)日：2011-06-15

申请号：EP10187012.9

申请日：2010-10-08

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78

CPC分类号： G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/42356 ,  H01L29/7841

摘要： The invention relates to a method of controlling a DRAM memory cell consisting of an FET transistor on a semiconductor-on-insulator substrate comprising a thin film (3) of semiconductor material separated from a base substrate (1) by an insulating layer (2, BOX), the transistor having a channel (4) and two control gates, a front control gate (8, 11) being arranged on top of the channel (4) and separated from the latter by a gate dielectric (7, 10) and a back control gate (9, 12, 13, 17, 18) being arranged in the base substrate and separated from the channel (4) by the insulating layer (BOX), characterized in that, in a cell programming operation, the front control gate and the back control gate are used jointly by applying a first voltage to the front control gate and a second voltage to the back control gate, said first voltage being lower in amplitude than the voltage needed to program the cell when no voltage is applied to the back control gate.

摘要翻译： 本发明涉及（2控制DRAM存储器单元的FET晶体管的在包括半导体材料的薄膜（3）在绝缘层通过从基底基板（1）分离的半导体在绝缘体上的基板组成的方法， BOX），被布置成具有一个信道（4）和两个控制栅，一个前控制栅极（8，11）中的晶体管上的通道（4）的顶部，并通过栅极电介质（7从后者分离，10）和 背控制栅（9，12，13，17，18）被布置在所述基底基板，并且从通道（4）通过绝缘层（BOX），在该特点是，在一个单元编程操作，前控制分离 栅极和后控制栅极被施加第一电压施加到所述前控制栅极和一个第二电压施加到背控制栅极共同使用时，所述第一电压在幅度上比所述单元编程所需的电压是低级当没有电压被施加到 背控制栅极。

公开(公告)号：EP2381470A1

公开(公告)日：2011-10-26

申请号：EP10290217.8

申请日：2010-04-22

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard ,  Nguyen, Bich-Yen

IPC分类号： H01L21/8234 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/823462 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/0705 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/7881

摘要： The present invention relates to a semiconductor device, comprising a semiconductor-on-insulator, SeOI, structure comprising a substrate, an oxide layer on the substrate and a semiconductor layer on the oxide layer; with a field-effect-transistor, FET, wherein the FET comprises a channel region in the substrate; a dielectric being at least a part of the oxide layer of the SeOI structure; and a gate at least partially being a first part of the semiconductor of the SeOI structure.

摘要翻译： 本发明涉及一种半导体器件，包括绝缘体上半导体，SeOI，包括衬底，衬底上的氧化物层和氧化物层上的半导体层的结构; 具有场效应晶体管FET，其中所述FET包括在所述衬底中的沟道区域; 电介质是SeOI结构的氧化物层的至少一部分; 以及至少部分地是SeOI结构的半导体的第一部分的栅极。

公开(公告)号：EP2372716A1

公开(公告)日：2011-10-05

申请号：EP10175849.8

申请日：2010-09-08

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard ,  Ngiyen, Bich-Yen

IPC分类号： G11C8/08 ,  G11C11/408 ,  H01L27/12 ,  H01L21/84 ,  H01L29/786

CPC分类号： G11C8/08 ,  H01L29/78609 ,  H01L29/78648

摘要： The invention according to a first aspect relates to a circuit made on a semiconductor-on-insulator substrate comprising a thin layer of semiconducting material separated from a base substrate by an insulator layer, including a transistor of a first type of channel in series with a transistor of a second type of channel between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in a thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel,
characterized in that each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased for modulating the threshold voltage of the transistor,
and in that at least one of the transistors is configured in order to operate in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.

摘要翻译： 根据第一方面的发明涉及在绝缘体上半导体衬底上制造的电路，其包括通过绝缘体层与基底衬底分离的半导体材料薄层，包括与第一类型沟道串联的第一类型沟道的晶体管 用于施加电源电位的第一和第二端子之间的第二类型的沟道的晶体管，每个晶体管包括在薄层中的漏极区域和源极区域，在源极区域和漏极区域之间延伸的沟道，以及 位于通道上方的前控制门，其特征在于，每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置用于调制晶体管的阈值电压，并且因为至少一个 晶体管被配置为在充分调制其阈值vo的背栅信号的作用下以耗尽模式工作 ltage。

公开(公告)号：EP2365520A2

公开(公告)日：2011-09-14

申请号：EP11156833.3

申请日：2011-03-03

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard ,  Nguyen, Bich-Yen

IPC分类号： H01L21/8244 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12 ,  G11C11/412

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/84 ,  H01L27/1203

摘要： The invention relates to an SRAM-type memory cell comprising:
- a semiconductor on insulator substrate comprising a thin film (1) of semiconductor material separated from a base substrate (2) by an insulating (BOX) layer;
- six transistors (T1-T6), comprising two access transistors (T1, T4), two conduction transistors (T2, T5) and two charge transistors (T3, T6) arranged so as to form with said conduction transistors (T2, T5) two back-coupled inverters,

characterized in that each of the transistors (T1-T6) has a back control gate (BG1, BG2) formed in the base substrate (2) below the channel and able to be biased in order to modulate the threshold voltage of the transistor, a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential, the first and second potentials being modulated according to the type of cell control operation.

摘要翻译： 本发明涉及一种SRAM型存储单元，包括： - 绝缘体上半导体衬底，包括通过绝缘（BOX）层从基底衬底（2）分离的半导体材料薄膜（1） - 包括两个存取晶体管（T1，T4），两个导电晶体管（T2，T5）和两个电荷晶体管（T3，T6）的六个晶体管（T1-T6），其布置成与所述导电晶体管（T2，T5）形成， 两个反耦合反相器，其特征在于，每个晶体管（T1-T6）具有形成在通道下方的基底衬底（2）中的后控制栅极（BG1，BG2），并且能够被偏置以便调制阈值 晶体管的电压，将存取晶体管的背控制栅极连接到第一电位的第一背栅极线和将导通晶体管的背控制栅极和电荷晶体管连接到第二电位的第二背栅极线，第一和第二 根据细胞控制操作的类型调节电位。

公开(公告)号：EP2355143A1

公开(公告)日：2011-08-10

申请号：EP11150845.3

申请日：2011-01-13

申请人： S.O.I.Tec Silicon on Insulator Technologies

发明人： Mazure, Carlos ,  Ferrant, Richard

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10873 ,  H01L29/732 ,  H01L29/7841 ,  H01L29/78639

摘要： According to a first aspect, the invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate comprising a thin layer (1) of semiconductor material separated from a base substrate (2) by means of a buried insulating layer (3, BOX), the device comprising a first conducting region (4, D1, S, E) in the thin layer and a second conducting region (5, BL, SL, lL) in the base substrate and being characterized by a contact (l1, 12, l N , lp) connecting the first region to the second region through the insulating layer.
According to a second aspect, the invention relates to a process for fabricating a semiconductor device according to its first aspect.

摘要翻译： 。根据一个第一方面，本发明（2）通过3掩埋绝缘层的手段（涉及在包括从基部衬底隔离的半导体材料薄层（1）的半导体绝缘体上的基板制造的半导体器件中， BOX），该装置包括一个第一导电区域（4，D1，S，E）在所述薄层与在基础基板的第二导电区域（5，BL，SL，LL），并通过一个接触的特征在于（L1， 12，L N，LP）通过绝缘层连接第一区域到第二区域。 。根据第二方面，本发明涉及一种用于半导体器件制造gemäß其第一方面。