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1.发明授权ADDRESS GENERATING DEVICE FOR USE IN MULTI-STAGE CHANNEL INTERLEAVER/DEINTERLEAVER 有权地址发生装置用在多级信道交织器/解交织器
公开(公告)号：EP1203452B1
公开(公告)日：2008-09-17
申请号：EP00942514.1
申请日：2000-07-13
发明人： SU, Sung-Il , KIM, Beong-Jo
IPC分类号： H03M13/27
CPC分类号： H03M13/2764 , H03M13/271
摘要： An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter count to B-1, outputs the 0 value when the first row address is outputting, outputs the added value of offset value F and previous output value of the row counter, and generates a counter reset signal when output the carry signal. The B is the number of rows. A column counter increases a count value in increments of one in response to the carry signal. A mapper permutates the output of the counter according to a predetermined permutation rule. An adder generates a read address by using the output of the row counter as the most significant bits (MSB) of the read address and by using the output of the mapper as the least significant bits (LSB) of the read address.
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2.发明公开ADDRESS GENERATING DEVICE FOR USE IN MULTI-STAGE CHANNEL INTERLEAVER/DEINTERLEAVER 有权地址发生装置用在多级信道交织器/解交织器
公开(公告)号：EP1203452A1
公开(公告)日：2002-05-08
申请号：EP00942514.1
申请日：2000-07-13
发明人： SU, Sung-Il , KIM, Beong-Jo
IPC分类号： H03M13/27
CPC分类号： H03M13/2764 , H03M13/271
摘要： An address generating device for addressing data stored in an interleaver memory in B rows and F columns, where F is not 2k for a positive integer k. A row counter being responsive to B clock pulses, outputs carry signal when the row counter count to B-1, outputs the 0 value when the first row address is outputting, outputs the added value of offset value F and previous output value of the row counter, and generates a counter reset signal when output the carry signal. The B is the number of rows. A column counter increases a count value in increments of one in response to the carry signal. A mapper permutates the output of the counter according to a predetermined permutation rule. An adder generates a read address by using the output of the row counter as the most significant bits (MSB) of the read address and by using the output of the mapper as the least significant bits (LSB) of the read address.
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