公开(公告)号：EP0471544A2

公开(公告)日：1992-02-19

申请号：EP91307426.6

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： Slemmer, William Carl ,  Coker, Thomas Allyn ,  McClure, David Charles

IPC: G06F11/26 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701 ,  G01R31/31719 ,  G11C7/1045

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Abstract translation: 公开了具有正常操作模式和特殊操作模式（诸如特殊测试模式）的集成电路。 特殊测试模式通过一系列信号启用，例如终端的过电压偏移，而不是单个这样的偏移，使得不经意地进入特殊测试模式的可能性较小，例如由于噪声或功率 降低和启动设备。 用于启用测试模式的电路包括一系列D型触发器，每个D型触发器在检测到过电压状态以及在另一个端子处施加的特定逻辑电平时被计时; 可以为多种特殊测试模式提供多个触发器系列。 此外，可以使用顺序码用于进一步的安全性。 公开了用于评估从多个地址终端并行接收的代码序列的逻辑以及在单个地址端子处接收的序列码序列。 附加功能包括提供上电复位电路，该电路在器件上电期间锁定进入测试模式。 进入测试模式的确认通过在器件未使能时在输出端子处呈现低阻抗来提供; 设备的芯片使能使设备退出测试模式。 一旦进入测试模式，器件的输出使能端可提供芯片使能功能。

公开(公告)号：EP0471544B1

公开(公告)日：1997-05-14

申请号：EP91307426.6

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： Slemmer, William Carl ,  Coker, Thomas Allyn ,  McClure, David Charles

IPC: G06F11/26 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701 ,  G01R31/31719 ,  G11C7/1045

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

公开(公告)号：EP0472266A2

公开(公告)日：1992-02-26

申请号：EP91304951.6

申请日：1991-05-31

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/34 ,  G11C29/38

Abstract: An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals. The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.

Abstract translation: 公开了一种具有并行测试读取模式的集成电路存储器。 存储器包括用于在并行读取模式期间逐位地比较多个数据字的比较器，用于使能或禁用输出缓冲器的比较结果。 在测试模式下，在并行测试比较失败的情况下，比较器使输出缓冲器进入高阻态; 对于通过并行测试，实际数据状态由输出端子呈现。 比较电路与输出数据路径并联，使得输出数据路径不受测试电路的不利影响，并且使得测试模式下的访问时间与正常操作期间的访问时间相同（假设通过 测试）。 该技术可以适用于广泛的并行测试方案。

公开(公告)号：EP0471541A2

公开(公告)日：1992-02-19

申请号：EP91307423.3

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G06F11/26 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled ; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Abstract translation: 公开了具有正常操作模式和特殊操作模式（诸如特殊测试模式）的集成电路。 特殊测试模式通过一系列信号启用，例如终端的过电压偏移，而不是单个这样的偏移，使得不经意地进入特殊测试模式的可能性较小，例如由于噪声或功率 降低和启动设备。 用于启用测试模式的电路包括一系列D型触发器，每个D型触发器在检测到过电压状态以及在另一个端子处施加的特定逻辑电平时被计时; 可以为多种特殊测试模式提供多个触发器系列。 附加功能包括提供上电复位电路，该电路在器件上电期间锁定进入测试模式。 进入测试模式的确认通过在器件未使能时在输出端子处呈现低阻抗来提供; 设备的芯片使能使设备退出测试模式。 一旦进入测试模式，器件的输出使能端可提供芯片使能功能。

公开(公告)号：EP0471541B1

公开(公告)日：1997-03-19

申请号：EP91307423.3

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G06F11/26 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701

公开(公告)号：EP0475588B1

公开(公告)日：1996-06-26

申请号：EP91307419.1

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G11C29/00

CPC classification number: G11C29/46

公开(公告)号：EP0471541A3

公开(公告)日：1992-12-23

申请号：EP91307423.3

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G06F11/26 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled ; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

公开(公告)号：EP0490680A2

公开(公告)日：1992-06-17

申请号：EP91311571.3

申请日：1991-12-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)

Inventor： Coker, Thomas Allyn ,  McClure, David Charles

IPC: G06F11/20

CPC classification number: G11C29/808 ,  G11C29/781 ,  G11C29/846

Abstract: An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.

Abstract translation: 公开了一种集成电路存储器，其包括与子阵列相关联的冗余列，并且其中多个输入/输出端子被放置成以读和写周期与子阵列中的多个列通信。 每个子阵列的冗余列数小于输入/输出端子的数量。 多路复用器将所选择的冗余列连接到所选择的读取放大器和写入电路，用于与更换的列相关联的输入/输出。 多路复用器包括连接到冗余列的位线的通过门和连接在每个通路之间的熔断器以及为冗余列选择的每个检测/写入电路。 与所选择的输入/输出不相关联的保险丝被打开，并且与选择的输入/输出相关联的保险丝保持原样。 预充电晶体管连接到通孔的保险丝侧，用于在通电门关闭之后对每个浮动节点进行预充电。 这种预充电否定了可能被陷在保险丝打开的那些线路的通孔的熔丝侧的任何电荷的影响，使得下一个周期的访问时间不会降低。

公开(公告)号：EP0472266B1

公开(公告)日：1997-07-30

申请号：EP91304951.6

申请日：1991-05-31

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Coker, Thomas Allyn

IPC: G11C29/00

CPC classification number: G11C29/28 ,  G11C29/34 ,  G11C29/38

公开(公告)号：EP0490680B1

公开(公告)日：1996-10-02

申请号：EP91311571.3

申请日：1991-12-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)

Inventor： Coker, Thomas Allyn ,  McClure, David Charles

IPC: G06F11/20

CPC classification number: G11C29/808 ,  G11C29/781 ,  G11C29/846

Abstract: An integrated circuit memory is disclosed which includes redundant columns associated with a sub-array, and in which multiple input/output terminals are placed in communication with multiple columns in the sub-array in read and write cycles. The number of redundant columns per sub-array is less than the number of input/output terminals. A multiplexer connects the selected redundant column to a selected sense amplifier and write circuit for the input/output with which the replaced column was associated. The multiplexer includes pass gates connected to the bit lines of the redundant column, and fuses connected between each of the pass gates and each of the sense/write circuits selectable for the redundant column. Those of the fuses which are not associated with the selected input/output are opened, and the fuses associated with the selected input/output are left intact. Precharge transistors are connected to the fuse sides of the pass gates, for precharging each of the floating nodes after the pass gates are turned off. This precharging negates the effect of any charge which may be trapped on the fuse side of the pass gates for those lines where the fuses are opened, so that the access time for the next cycle will not be degraded.