公开(公告)号：EP0547919B1

公开(公告)日：1998-08-05

申请号：EP92311612.3

申请日：1992-12-18

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G06F11/20

CPC classification number: G11C29/83 ,  G11C29/78

Abstract: An integrated circuit memory having redundant rows, for replacing a row in a primary array having a defective memory cell, is disclosed. For each primary row that is to be replaced, a fuse is opened between the output of the row decoder and the word line for the replaced row. A power-on reset circuit is provided in the memory for determining if the power supply voltage has reached an adequate voltage; if not, a transistor connected to each word line is turned on, biasing the word line to a de-energizing voltage. This ensures that the word lines for replaced rows do not power up in an "on" state.

公开(公告)号：EP0855650A1

公开(公告)日：1998-07-29

申请号：EP98200771.8

申请日：1994-04-20

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G06F11/20 ,  G11C29/00

CPC classification number: G11C29/785 ,  G11C8/06 ,  G11C29/44 ,  G11C29/88

Abstract: According to the present invention, one or more addresses are forced to a logic state to define a smaller, fully functional portion of embedded memory. A first preferred embodiment has a first fuse circuit and a second fuse circuit which control the conduction and the output signal of a transmission gate which passes through an address signal. The output signal of both the first and the second fuse circuits are input signals to logic circuitry which produces a first input signal and a second input signal to the transmission gate. When the first fuse is blown, the address signal is forced to a first logic state and when the second fuse is blown, the address signal is forced to a second logic state. When neither the first fuse nor the second fuse is blown, the address signal is simply passed through the transmission gate.
A second preferred embodiment of the present invention has a first fuse circuit, a second fuse circuit, and an inverting stage through which an address signal passes. When the first fuse is blown, the address signal is forced to a first logic state and when the second fuse is blown, the address signal is forced to a second logic state. When neither the first fuse nor the second fuse is blown, the address signal is inverted.

Abstract translation: 根据本发明，一个或多个地址被强制为逻辑状态以限定嵌入式存储器的较小的，完全功能的部分。 第一优选实施例具有第一熔丝电路和第二熔丝电路，其控制通过地址信号的传输门的传导和输出信号。 第一和第二熔丝电路的输出信号是输入信号到逻辑电路，其产生第一输入信号和第二输入信号到传输门。 当第一熔丝熔断时，地址信号被强制为第一逻辑状态，当第二熔丝熔断时，地址信号被强制为第二逻辑状态。 当第一熔丝和第二熔丝都不熔断时，地址信号就简单地通过传输门。 本发明的第二优选实施例具有第一熔丝电路，第二熔丝电路和地址信号通过的反相级。 当第一熔丝熔断时，地址信号被强制为第一逻辑状态，当第二熔丝熔断时，地址信号被强制为第二逻辑状态。 当第一个保险丝和第二个保险丝都不熔断时，地址信号被反转。

公开(公告)号：EP0471544B1

公开(公告)日：1997-05-14

申请号：EP91307426.6

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： Slemmer, William Carl ,  Coker, Thomas Allyn ,  McClure, David Charles

IPC: G06F11/26 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/46 ,  G01R31/31701 ,  G01R31/31719 ,  G11C7/1045

Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. In addition, sequential codes may be used for further security. Logic for evaluating both a sequence of codes received in parallel from a number of address terminals, and also a sequence of serial codes received at single address terminal, are disclosed. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

公开(公告)号：EP0471542B1

公开(公告)日：1997-03-12

申请号：EP91307424.1

申请日：1991-08-12

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G06F1/24 ,  G06F11/267 ,  G11C7/00 ,  G11C29/00 ,  H03K3/037 ,  H03K3/356

CPC classification number: G11C7/22 ,  G01R31/31701 ,  G06F1/24 ,  G11C29/46 ,  H03K3/0375 ,  H03K3/356008

公开(公告)号：EP0390452B1

公开(公告)日：1997-03-05

申请号：EP90303170.6

申请日：1990-03-23

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Lysinger, Mark Alan

IPC: H03K3/037 ,  H03K23/50 ,  H04J3/06

CPC classification number: H04J3/0626

公开(公告)号：EP0646926A3

公开(公告)日：1995-11-15

申请号：EP94307068.0

申请日：1994-09-28

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: An edge transition detector for a static access memory integrated circuit provides programmable operating characteristics. The edge transition detector includes a delay line taking a state signal received on a signal line as an input and generating a delayed state signal. An exclusive-OR gate takes the state signal and the delayed state signal as inputs and generating a transition pulse signal. An edge transition detector enable line connected to the exclusive-OR gate forces the output level of the exclusive-OR gate to match a predetermined logic level in a power efficient manner. An output buffer taking the transition pulse signal as its input and generating an edge detection pulse signal may also be modified to fusing, mask programming, or bonding to eliminate the edge transition detection signal.

公开(公告)号：EP0675439A1

公开(公告)日：1995-10-04

申请号：EP94308981.3

申请日：1994-12-02

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles ,  Slemmer, William Carl

IPC: G06F11/20 ,  G11C29/00

CPC classification number: G11C29/785 ,  G11C29/24

Abstract: Therefore, according to the present invention, fuse circuitry is presented which emulates fuse blowing in a temporary manner. As an embodiment, redundant elements of an integrated circuit may be enabled and/or tested prior to laser repair through the use of non-destructive fuse circuitry which emulates fuse blowing. An integrated circuit has a plurality of addressable elements and a plurality of redundant elements, which may be used to replace defective addressable elements. Each redundant element has a non-destructive fuse circuit associated with it which may be used to enable and/or test the redundant element prior to laser repair by emulating the blowing of a fuse contained in the non-destructive fuse circuit. The non-destructive fuse circuit is comprised of a fuse connected to a control logic means, such as an inverter, wherein the control logic means is in turn controlled by a test signal. Emulation of blowing the fuse or not blowing the fuse is accomplished by the logic level of the test signal. So, rather than connecting the fuse to a power supply, the fuse is connected to the control logic means which is controlled by the test signal. Thus, non-destructive enabling and testing of a redundant element prior to laser repair may be accomplished by emulating blowing or not blowing of the fuse through the control logic means. The fuse can then be permanently blown if desired.

Abstract translation: 因此，根据本发明，提供了以临时方式模拟熔丝熔断的熔丝电路。 作为实施例，集成电路的冗余元件可以在激光修复之前通过使用模拟保险丝熔断的非破坏性熔丝电路来启用和/或测试。 集成电路具有多个可寻址元件和多个冗余元件，其可用于替换有缺陷的可寻址元件。 每个冗余元件具有与其相关联的非破坏性熔丝电路，其可以用于通过模拟非破坏性熔丝电路中包含的熔丝的熔化来在激光修复之前启用和/或测试冗余元件。 非破坏性熔丝电路包括连接到控制逻辑装置（例如逆变器）的熔丝，其中控制逻辑装置又由测试信号控制。 对保险丝进行熔断或不熔断保险丝的仿真是通过测试信号的逻辑电平实现的。 因此，不是将保险丝连接到电源，而是将熔丝连接到由测试信号控制的控制逻辑装置。 因此，在激光修复之前的冗余元件的无损使能和测试可以通过模拟通过控制逻辑装置的熔丝的吹送或不吹动来实现。 如果需要，保险丝可以永久吹塑。

公开(公告)号：EP0565284A3

公开(公告)日：1995-04-19

申请号：EP93302376.4

申请日：1993-03-26

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： Lysinger, Mark A. ,  Slemmer, William Carl ,  Brady, James ,  McClure, David Charles

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A memory is disclosed having a plurality of memory cells in a memory array arranged in rows and columns, each of the memory cells capable of storing a logic state therein. Each pair of bit lines is associated with one of the columns. A column decoder selects a column in the array responsive to a column address. A plurality of word line drivers selects, in response to a row address, a row of memory cells for connection with their associated pair of bit lines. A plurality of row isolation circuits isolates and enables a selected group of memory cells of each row from the remainder of the row in response to a bulk write signal. Each row isolation circuit has a conduction path between its associated word line driver and the selected memory cells in the associated row. A bulk write signal is sent to each column containing the selected memory cells. A first logic state is then written into the selected memory cells in response to the bulk write signal.

公开(公告)号：EP0632594A2

公开(公告)日：1995-01-04

申请号：EP94304643.3

申请日：1994-06-27

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/003

CPC classification number: H03K19/0013

Abstract: An output driver includes a pull-up and a pull-down transistor in series between an upper and a lower power supply voltage. Each transistor is controlled by a latch connected to its gate. Control transistors are cross-coupled between inputs to the latches and a power supply voltage to force at least one of the latches to be in a known state. This prevents both of the transistors from turning on simultaneously.

Abstract translation: 锁存控制输出驱动器电路具有包括上拉和下拉晶体管的输出驱动器电路。 上拉晶体管具有连接到上电源电压的漏极和连接到下拉晶体管的漏极的源极。 下拉晶体管具有连接到较低电源电压的源极。 锁存电路的输出连接到上拉晶体管的栅极。 具有连接到下拉晶体管的栅极的第二锁存电路的输出。 锁存电路接收两个逆变器的输入。 两个控制晶体管的源极连接到上电源电压。 第一个漏极连接到第一个锁存电路输入，第二个与第一个锁存电路的漏极连接。 两个晶体管的栅极连接到两个锁存电路中的另一个。

公开(公告)号：EP0554052A3

公开(公告)日：1994-12-14

申请号：EP93300560.5

申请日：1993-01-27

Applicant: SGS-THOMSON MICROELECTRONICS, INC.

Inventor： McClure, David Charles

IPC: G06F11/20

CPC classification number: G11C29/84

Abstract: An integrated circuit memory is disclosed which has its primary memory array arranged into blocks and which has redundant columns, each of which can replace a column in any one of the blocks. The redundant columns are selected by way of a redundant column decoder, associated with each column. A plurality of redundant sense amplifiers are each associated with selected redundant columns. Each of the redundant column decoders includes a set of address fuses for storing the column address responsive to which its associated redundant column is to be selected, and which are in series with pass gates which are turned on when redundancy is enabled, and turned off otherwise. This arrangement of address fuses and pass gates reduces and balances the loading of the decoder on the address lines, may be implemented with fewer transistors and thus in reduced chip area relative to conventional decoders, and also reduces the propagation delay through the decoder. The coupling of each redundant sense amplifier is controlled by a redundant multiplexer associated with each of the input/output terminals. Each redundant multiplexer receives the redundant column select signals from each redundant column decoder corresponding thereto, and includes fuses which indicate if its input/output terminal is to be placed in communication with its associated sense amplifier upon selection of a redundant column.