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公开(公告)号：EP0908938B1
公开(公告)日：2002-12-04
申请号：EP98307803.1
申请日：1998-09-25
发明人： Gruening, Ulrike , Beintner, Jochen , Radens, Carl
IPC分类号： H01L21/31 , H01L21/762 , H01L21/763
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31 , H01L21/763 , H01L27/10867 , Y10S438/97
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2.发明公开DRAM trench capacitor and method of fabricating the same 审中-公开Graben-KondensatorfürDRAM und Verfahren zur Herstellung desselben
公开(公告)号：EP0962972A1
公开(公告)日：1999-12-08
申请号：EP99304168.0
申请日：1999-05-28
发明人： Economikos, Laertis , Gruening, Ulrike , Ho, Herbert L. , Radens, Carl J. , Jammy, Ragarao , Hoepfner, Joachim , Shen, Hua
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sidewall, growing a layer of oxide (16) on the upper portion of the sidewall, removing the remainder of the layer of dielectric material, doping to form a buried plate (17), forming a node dielectric (18), and forming an inner electrode (19) within the trench. The oxide layer at the upper portion of the trench is preferably formed by a LOCOS technique.
摘要翻译： 通过在半导体衬底（10）的表面上蚀刻沟槽（11）形成用于深沟槽存储电容器的存储节点，在沟槽的侧壁上形成电介质层（14），部分地去除 电介质材料以暴露侧壁的上部，在侧壁的上部生长一层氧化物（16），去除电介质材料层的其余部分，掺杂以形成掩埋板（17），形成 节点电介质（18），并且在所述沟槽内形成内部电极（19）。 沟槽上部的氧化物层优选通过LOCOS技术形成。
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3.发明授权Method of providing low-resistance salicide fill for trench capacitors 有权一种用于电容器严重Salizidfüllung低电阻过程
公开(公告)号：EP0967643B1
公开(公告)日：2006-12-13
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
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公开(公告)号：EP0949674A3
公开(公告)日：2003-07-02
申请号：EP99302567.5
申请日：1999-03-31
发明人： Gruening, Ulrike , Jaiprakash, Venkatachalam C. , Bronner, Gary , Radens, Carl c/o IBM Corporation , Beintner, Jochen
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： The invention relates to reducing variations in thickness and height of the buried strap of a trench capacitor. Reduced variations in thickness and height is achieved by defining the top of the buried strap by recessing the poly (112) in the trench to the top of the buried strap. The collar (110) is then recessed to below the top surface to define the bottom of the buried strap. A poly layer (122) is deposited to line the sidewalls of the trench top surface of the poly trench fill, and recessed region above the collar. A etch is then used to remove the excess poly layer from the sidewalls and top surface of the poly trench fill, leaving the recessed region above the collar filled to form the buried strap. The etch removes the poly in the vertical and horizontal direction at about the same rate.
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5.发明公开Low-resistance salicide fill for trench capacitors 有权Verfahren zurSalizidfüllungmit Niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A2
公开(公告)日：1999-12-29
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
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公开(公告)号：EP0908938A3
公开(公告)日：1999-12-15
申请号：EP98307803.1
申请日：1998-09-25
发明人： Gruening, Ulrike , Beintner, Jochen , Radens, Carl
IPC分类号： H01L21/31 , H01L21/314 , H01L21/033 , H01L21/762
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31 , H01L21/763 , H01L27/10867 , Y10S438/97
摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.
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7.发明公开Low-resistance salicide fill for trench capacitors 有权Salizidfüllungmit niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A3
公开(公告)日：2003-08-20
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide (32) as a component of the trench electrode (26,32,34) in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
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8.发明公开Method of forming buried strap for trench capacitor 审中-公开Verfahren zur Herstellung eines vergrabenen Verbindungsstreifensfüreinen Grabenkondensator
公开(公告)号：EP0949674A2
公开(公告)日：1999-10-13
申请号：EP99302567.5
申请日：1999-03-31
发明人： Gruening, Ulrike , Jaiprakash, Venkatachalam C. , Bronner, Gary , Radens, Carl , Beintner, Jochen
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： The invention relates to reducing variations in thickness and height of the buried strap of a trench capacitor. Reduced variations in thickness and height is achieved by defining the top of the buried strap by recessing the poly in the trench to the top of the buried strap. The collar is then recessed to below the top surface to define the bottom of the buried strap. A poly layer is deposited to line the sidewalls of the trench top surface of the poly trench fill, and recessed region above the collar. A etch is then used to remove the excess poly layer from the sidewalls and top surface of the poly trench fill, leaving the recessed region above the collar filled to form the buried strap. The etch removes the poly in the vertical and horizontal direction at about the same rate.
摘要翻译： 本发明涉及减小沟槽电容器的掩埋带的厚度和高度的变化。 通过将沟槽中的多孔凹入掩埋带的顶部来限定掩埋带的顶部来实现厚度和高度的减小。 然后将套环凹入到顶部表面下方以限定掩埋带的底部。 沉积聚层以使多沟槽填充物的沟槽顶表面的侧壁和套环上方的凹陷区域对齐。 然后使用蚀刻从多沟槽填充物的侧壁和顶表面去除多余的多晶硅层，从而使填充的套环上方的凹陷区域形成掩埋带。 该蚀刻以大致相同的速率在垂直和水平方向上去除多晶。
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公开(公告)号：EP0908938A2
公开(公告)日：1999-04-14
申请号：EP98307803.1
申请日：1998-09-25
发明人： Gruening, Ulrike , Beintner, Jochen , Radens, Carl
IPC分类号： H01L21/31 , H01L21/314 , H01L21/033 , H01L21/762
CPC分类号： H01L27/1087 , H01L21/3081 , H01L21/31 , H01L21/763 , H01L27/10867 , Y10S438/97
摘要： A pad layer disposed on a semiconductor substrate 102 and a buffer layer 108 disposed within the pad layer such that the pad layer is divided into a dielectric layer 106 below the buffer layer and a mask layer 110 above the buffer layer. A method of forming layers with uniform planarity and thickness on a semiconductor chip includes the steps of providing a substrate having a thermal pad 106 formed thereon, forming a dielectric layer 106 on the thermal pad, forming a buffer layer 108 on the dielectric layer wherein the buffer layer is made from a different material than the dielectric layer and forming a mask layer 110 on the buffer layer wherein the buffer layer is made from a different material than the mask layer.
摘要翻译： 设置在半导体衬底102上的衬垫层和设置在衬垫层内的缓冲层108，使得衬垫层被分成缓冲层下方的介电层106和缓冲层上方的掩模层110。 在半导体芯片上形成具有均匀平面性和厚度的层的方法包括以下步骤：提供其上形成有热垫106的衬底;在热垫上形成介电层106;在介电层上形成缓冲层108，其中 缓冲层由与介电层不同的材料制成并且在缓冲层上形成掩模层110，其中缓冲层由与掩模层不同的材料制成。
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公开(公告)号：EP1073115A3
公开(公告)日：2004-08-04
申请号：EP00306332.8
申请日：2000-07-25
发明人： Gruening, Ulrike , Radens, Carl J. , Tobben, Dirk
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A process for manufacturing a deep trench capacitor in a trench (10). The capacitor comprises a collar (18) in an upper region of the trench and a buried plate (26) in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material (16) such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
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