公开(公告)号：EP0962972A1

公开(公告)日：1999-12-08

申请号：EP99304168.0

申请日：1999-05-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  SIEMENS AKTIENGESELLSCHAFT

发明人： Economikos, Laertis ,  Gruening, Ulrike ,  Ho, Herbert L. ,  Radens, Carl J. ,  Jammy, Ragarao ,  Hoepfner, Joachim ,  Shen, Hua

IPC分类号： H01L21/8242

CPC分类号： H01L27/10861

摘要： A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sidewall, growing a layer of oxide (16) on the upper portion of the sidewall, removing the remainder of the layer of dielectric material, doping to form a buried plate (17), forming a node dielectric (18), and forming an inner electrode (19) within the trench. The oxide layer at the upper portion of the trench is preferably formed by a LOCOS technique.

摘要翻译： 通过在半导体衬底（10）的表面上蚀刻沟槽（11）形成用于深沟槽存储电容器的存储节点，在沟槽的侧壁上形成电介质层（14），部分地去除 电介质材料以暴露侧壁的上部，在侧壁的上部生长一层氧化物（16），去除电介质材料层的其余部分，掺杂以形成掩埋板（17），形成 节点电介质（18），并且在所述沟槽内形成内部电极（19）。 沟槽上部的氧化物层优选通过LOCOS技术形成。

公开(公告)号：EP0923113A2

公开(公告)日：1999-06-16

申请号：EP98309445.9

申请日：1998-11-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Economikos, Laertis ,  Murthy, Cheruvu S. ,  Shen, Hua

IPC分类号： H01L21/225 ,  H01L21/334 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L21/2255 ,  H01L29/945 ,  Y10S438/92

摘要： Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by:

(a) applying a dopant-containing oxide glass layer (60) on the semiconductor surface (61),
(b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer (62),
(c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and
(d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass.
The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

摘要翻译： 通过：（a）在半导体表面（61）上施加含掺杂剂的氧化物玻璃层（60），（b）将掺杂剂掺杂剂半导体封装在掺杂剂半导体区域中， （62），（c）在非氧化气氛中加热来自步骤（b）的衬底，由此玻璃中的至少一部分掺杂剂在半导体表面扩散到衬底中 ，和（d）在氧化气氛中加热来自步骤（c）的玻璃涂覆的基材，由此在半导体表面附近的玻璃中的至少一部分掺杂剂被迫通过氧气扩散通过半导体表面 玻璃。 该方法对于将半导体衬底中的掩模板制成可用于沟槽电容器结构中是特别有用的。 优选的半导体衬底材料是单晶硅。 优选的掺杂剂是砷。

公开(公告)号：EP1132949A3

公开(公告)日：2004-10-06

申请号：EP01302263.7

申请日：2001-03-12

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Shen, Hua ,  Athavale, Satish ,  Economikos, Laertis ,  Kunkel, Gerhard ,  Kotecki, David ,  LIAN, Jenny ,  Jamin, Fen F. ,  CHAUDHARY, Nirmal

IPC分类号： H01L21/02 ,  H01L21/768

CPC分类号： H01L21/7687 ,  H01L21/76885 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

公开(公告)号：EP0923113A3

公开(公告)日：2004-09-08

申请号：EP98309445.9

申请日：1998-11-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Economikos, Laertis ,  Murthy, Cheruvu S. ,  Shen, Hua

IPC分类号： H01L21/225 ,  H01L21/334 ,  H01L29/94

CPC分类号： H01L29/66181 ,  H01L21/2255 ,  H01L29/945 ,  Y10S438/92

摘要： Doped semiconductor with high dopant concentrations in small semiconductor regions without excess spreading of the doped region are formed by: (a) applying a dopant-containing oxide glass layer (60) on the semiconductor surface (61), (b) capping the dopant-containing oxide glass layer with a conformal silicon oxide layer (62), (c) heating the substrate from step (b) in a non-oxidizing atmosphere whereby at least a portion of the dopant in the glass diffuses into the substrate at the semiconductor surface, and (d) heating the glass-coated substrate from step (c) in an oxidizing atmosphere whereby at least a portion of the dopant in the glass near the semiconductor surface is forced into the substrate at the semiconductor surface by diffusion of oxygen through the glass. The method is especially useful for making buried plates in semiconductor substrates which may be used in trench capacitor structures. The preferred semiconductor substrate material is monocrystalline silicon. The preferred dopant is arsenic.

公开(公告)号：EP1132949A2

公开(公告)日：2001-09-12

申请号：EP01302263.7

申请日：2001-03-12

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Shen, Hua ,  Athavale, Satish ,  Economikos, Laertis ,  Kunkel, Gerhard ,  Kotecki, David ,  LIAN, Jenny ,  Jamin, Fen F. ,  CHAUDHARY, Nirmal

IPC分类号： H01L21/02

CPC分类号： H01L21/7687 ,  H01L21/76885 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

摘要： A method for forming an electrode. The method includes forming a conductive plug through a first dielectric layer. The plug extends from an upper surface of the first dielectric layer to a contact region in a semiconductor substrate. The electrode is formed photolithographically, misalignment of a mask registration in the photolithography resulting in exposing surface portions of the barrier contact. A second dielectric layer is deposited over the first dielectric layer, over side portions and top portions of the formed electrode, and over the exposed portions of barrier contact. A sacrificial material is provided on portions of the second dielectric layer disposed on lower sides of the electrode, on portions of the second dielectric layer disposed on the first dielectric layer, and on said exposed portions of the barrier contact while exposing portions of the second dielectric layer on the top portions and upper side portions of the formed electrode. The exposed portions of the second dielectric layer are removed while leaving the portions of the second dielectric layer on the exposed portions of the barrier contact. A material is deposited over exposed portions of the first electrode and over remaining portions of the second dielectric layer in an oxidizing environment. A second electrode is formed for the storage element over the material. In forming a capacitor storage element, the portion of the second dielectric layer on the barrier contact prevents oxidation of the barrier contact during the material formation process.

摘要翻译： 一种形成电极的方法。 该方法包括通过第一电介质层形成导电插塞。 插头从第一电介质层的上表面延伸到半导体衬底中的接触区域。 光刻光刻形成电极，在光刻中使掩模配准不对准，导致暴露屏障接触的表面部分。 第二电介质层沉积在第一电介质层上，在形成的电极的侧面部分和顶部上方以及屏障接触的暴露部分之上。 牺牲材料设置在设置在电极的下侧上的第二电介质层的部分上，在设置在第一电介质层上的第二电介质层的部分上以及在屏蔽接触的所述暴露部分上，同时暴露第二电介质的部分 在所形成的电极的顶部和上侧部分上。 第二电介质层的暴露部分被去除，同时将第二电介质层的部分留在屏障接触的暴露部分上。 在氧化环境中将材料沉积在第一电极的暴露部分和第二电介质层的剩余部分上。 在材料上形成用于存储元件的第二电极。 在形成电容器存储元件时，屏障接触部分上的第二电介质层在材料形成过程中防止了屏障接触的氧化。

公开(公告)号：EP0929099A3

公开(公告)日：1999-09-08

申请号：EP98310213.8

申请日：1998-12-14

申请人： International Business Machines Corporation

发明人： Arndt, Kenneth C. ,  Conti, Richard A. ,  Dobuzinski, David M. ,  Economikos, Laertis ,  Gambino, Jeffrey P. ,  Hoh, Peter D. ,  Narayan, Chandrasekhar

IPC分类号： H01L21/768 ,  H01L21/3213

CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

摘要： Stresses commonly induced in dielectrics of integrated circuits manufactured using metal patterning methods, can be reduced by rounding the lower corners associated with features formed as part of the integrated circuit before applying the outer layer. For metal lines patterned by RIE, corners can be rounded using a two-step metal etching process: a first step producing a vertical sidewall and a second step tapering lower portions of the vertical sidewall or producing a tapered spacer along its lower portions. This produces a rounded bottom corner which improves the step coverage of the overlying dielectric, and eliminates the potential for cracks. For metal lines patterned by damascene, corners can be rounded using a two-step trench etching process: a first step producing a vertical sidewall, and a second step producing a tapered sidewall along its lower portions.

摘要翻译： 在使用金属图案化方法制造的集成电路的电介质中通常引起的应力可以通过在施加外层之前将与作为集成电路的一部分形成的特征相关联的下拐角四舍五入来减小。 对于通过RIE图案化的金属线，拐角可以使用两步金属蚀刻工艺来圆化：产生垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细或沿着其下部产生锥形间隔物的第二步骤。 这产生了一个圆形的底部拐角，它改善了上覆电介质的台阶覆盖，并消除了裂纹的可能性。 对于通过镶嵌图案化的金属线，角部可以使用两步式沟槽蚀刻工艺来圆化：产生垂直侧壁的第一步骤和沿着其下部部分产生锥形侧壁的第二步骤。

公开(公告)号：EP0929099A2

公开(公告)日：1999-07-14

申请号：EP98310213.8

申请日：1998-12-14

申请人： International Business Machines Corporation

发明人： Arndt, Kenneth C. ,  Conti, Richard A. ,  Dobuzinski, David M. ,  Economikos, Laertis ,  Gambino, Jeffrey P. ,  Hoh, Peter D. ,  Narayan, Chandrasekhar

IPC分类号： H01L21/768 ,  H01L21/3213

CPC分类号： H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

摘要： Stresses commonly induced in dielectrics of integrated circuits manufactured using metal patterning methods, can be reduced by rounding the lower corners associated with features formed as part of the integrated circuit before applying the outer layer. For metal lines patterned by RIE, corners can be rounded using a two-step metal etching process: a first step producing a vertical sidewall and a second step tapering lower portions of the vertical sidewall or producing a tapered spacer along its lower portions. This produces a rounded bottom corner which improves the step coverage of the overlying dielectric, and eliminates the potential for cracks. For metal lines patterned by damascene, corners can be rounded using a two-step trench etching process: a first step producing a vertical sidewall, and a second step producing a tapered sidewall along its lower portions.

摘要翻译： 在使用金属图案化方法制造的集成电路的电介质中通常引起的应力可以通过在施加外层之前将形成为集成电路的一部分的特征相关联的下角四舍五入来减少。 对于通过RIE图案化的金属线，角部可以使用两步金属蚀刻工艺圆化：第一步骤，产生垂直侧壁，第二阶段使垂直侧壁的下部逐渐变细，或沿其下部产生锥形间隔物。 这产生了圆角的底角，其改善了上覆电介质的台阶覆盖，并消除了裂纹的可能性。 对于由大马士革图案化的金属线，角部可以使用两步沟槽蚀刻工艺圆化：产生垂直侧壁的第一步骤，以及沿其下部分产生锥形侧壁的第二步骤。