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1.发明公开DRAM trench capacitor and method of fabricating the same 审中-公开Graben-KondensatorfürDRAM und Verfahren zur Herstellung desselben
公开(公告)号：EP0962972A1
公开(公告)日：1999-12-08
申请号：EP99304168.0
申请日：1999-05-28
发明人： Economikos, Laertis , Gruening, Ulrike , Ho, Herbert L. , Radens, Carl J. , Jammy, Ragarao , Hoepfner, Joachim , Shen, Hua
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： A storage node for deep trench-based storage capacitor is formed by etching a trench (11) in a surface of a semiconductor substrate (10), forming a layer of dielectric (14) on a sidewall of the trench, partially removing the layer of dielectric material in order to expose an upper portion of the sidewall, growing a layer of oxide (16) on the upper portion of the sidewall, removing the remainder of the layer of dielectric material, doping to form a buried plate (17), forming a node dielectric (18), and forming an inner electrode (19) within the trench. The oxide layer at the upper portion of the trench is preferably formed by a LOCOS technique.
摘要翻译： 通过在半导体衬底（10）的表面上蚀刻沟槽（11）形成用于深沟槽存储电容器的存储节点，在沟槽的侧壁上形成电介质层（14），部分地去除 电介质材料以暴露侧壁的上部，在侧壁的上部生长一层氧化物（16），去除电介质材料层的其余部分，掺杂以形成掩埋板（17），形成 节点电介质（18），并且在所述沟槽内形成内部电极（19）。 沟槽上部的氧化物层优选通过LOCOS技术形成。
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2.发明公开Low-resistance salicide fill for trench capacitors 有权Salizidfüllungmit niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A3
公开(公告)日：2003-08-20
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide (32) as a component of the trench electrode (26,32,34) in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
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3.发明授权Method of providing low-resistance salicide fill for trench capacitors 有权一种用于电容器严重Salizidfüllung低电阻过程
公开(公告)号：EP0967643B1
公开(公告)日：2006-12-13
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
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4.发明公开Low-resistance salicide fill for trench capacitors 有权Verfahren zurSalizidfüllungmit Niedrigem WiderstandfürGrabenkondensatoren
公开(公告)号：EP0967643A2
公开(公告)日：1999-12-29
申请号：EP99304729.9
申请日：1999-06-17
IPC分类号： H01L21/8242
CPC分类号： H01L27/10861
摘要： Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.
摘要翻译： 使用导致难熔金属硅化物作为沟槽的下部区域中的沟槽电极的部件的方法来制造沟槽电容器。 与具有类似尺寸的常规沟槽电极相比，含有自对接硅化物的沟槽电极显示出降低的串联电阻，从而能够减少接地规则存储器单元格和/或减少的单元访问时间。 本发明的沟槽电容器特别可用作DRAM存储单元的组件。
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公开(公告)号：EP1073115A3
公开(公告)日：2004-08-04
申请号：EP00306332.8
申请日：2000-07-25
发明人： Gruening, Ulrike , Radens, Carl J. , Tobben, Dirk
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A process for manufacturing a deep trench capacitor in a trench (10). The capacitor comprises a collar (18) in an upper region of the trench and a buried plate (26) in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material (16) such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
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6.发明公开Crystal-axis-aligned vertical side wall DRAM and process for manufacture thereof 审中-公开经由垂直对齐于侧壁的晶轴和方法及其制造DRAM
公开(公告)号：EP1071129A2
公开(公告)日：2001-01-24
申请号：EP00306232.0
申请日：2000-07-21
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/1087 , H01L27/10876
摘要： A dynamic random access memory (DRAM) cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench. The side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis. A process for manufacturing such a DRAM cell comprises: (a) forming a deep trench in a substrate, (b) forming a faceted crystal region along the trench side wall having a single crystallographic orientation, and (c) forming a transistor device partially disposed on the faceted crystal region in the side wall. The faceted crystal region may be formed by growing an oxide collar, such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes.
摘要翻译： 一种动态随机存取存储器（DRAM）单元，包括具有有源晶体管器件在沟槽的侧壁上部分地设置在深沟槽存储电容器。 侧壁对准于具有沿单个晶轴的结晶取向的第一结晶学平面。 制造寻求的DRAM单元的方法，包括：（a）形成在衬底的深沟槽，（b）中沿沟槽侧壁上形成具有单一晶体取向的小平面晶体区，以及（c）形成晶体管器件部分地设置 在侧壁上的小平面晶体区。 例如通过选择以促进沿着比沿第二家庭晶轴的晶轴的第一家庭更高的氧化速率氧化条件下的局部热氧化：所述小平面晶体区可以由氧化物轴环，颜色的生长来形成。
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7.发明公开
公开(公告)号：EP0929101A1
公开(公告)日：1999-07-14
申请号：EP98310525.5
申请日：1998-12-21
发明人： Bronner, Gary Bela , Gambino, Jeffrey P. , Mandelman, Jack A. , Radens, Carl J. , Tonti, William Robert
IPC分类号： H01L21/8234 , H01L21/336 , H01L21/28 , H01L21/225
CPC分类号： H01L21/28035 , H01L21/82345
摘要： Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.
摘要翻译： 通过在第一导电类型的栅极结构的至少一个侧壁上掺杂选择数量的具有自对准绝缘层的栅极结构的结构，从而提供栅极结构的阵列，从而提供一些栅极结构，从而提供双功能掺杂 掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的导电类型。 还提供了栅极结构的阵列，由此各个栅极结构在其顶部部分包含自对准绝缘层，并且其中一些栅极结构被掺杂有第一导电类型，并且其他栅极结构被掺杂有第二和不同的 导电类型。
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公开(公告)号：EP1039534A3
公开(公告)日：2001-04-04
申请号：EP00103845.4
申请日：2000-02-24
发明人： Gruening, Ulrike , Halle, Scott , Radens, Carl J. , Welser, Jeffrey J. , Beintner, Jochen , Mandelman, Jack A. , Wittmann, Juergen
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10864 , H01L27/10861
摘要： A method includes forming a trench capacitor in a semiconductor body. A recess is formed in the upper portion of the capacitor with such recess having sidewalls in the semiconductor body. A first material is deposited over the sidewalls and over a bottom of the recess. A second material is deposited over the first material. A mask is provided over the second material. The mask has: a masking region to cover one portion of said recess bottom; and a window over a portion of said recess sidewall and another portion of said recess bottom to expose underlying portions of the second material. Portions of the exposed underlying portions of the second material are selectively removing while leaving substantially un-etched exposed underlying portions of the first material. The exposed portions of the first material and underlying portions of the semiconductor body are selectively removed. An isolation region is formed in the removed portions of the semiconductor body. The mask is provided over the second material with a masking region covering one portion of said recess sidewall and one portion of said recess bottom and with a window disposed over an opposite portion of said recess sidewall and an opposite portion of said recess bottom to expose underlying portions of the second material. Etching is provided into the exposed underlying portions of the semiconductor body to form a shallow trench in the semiconductor body. An insulating material is formed in the shallow trench to form a shallow trench isolation region. With such method, greater mask misalignment tolerances are permissible.
摘要翻译： 一种方法包括在半导体本体中形成沟槽电容器。 在电容器的上部形成凹部，在半导体本体中具有侧壁。 第一材料沉积在凹槽的侧壁和底部上方。 第二种材料沉积在第一种材料上。 在第二材料上提供掩模。 掩模具有：掩蔽区域，以覆盖所述凹部底部的一部分; 以及位于所述凹陷侧壁的一部分上的窗口和所述凹陷底部的另一部分以暴露第二材料的下部。 第二材料的暴露下面的部分的部分是选择性地去除，同时留下第一材料的基本上未蚀刻的暴露的下部。 选择性地去除半导体主体的第一材料和下部的暴露部分。 在半导体本体的去除部分中形成隔离区。 所述掩模设置在所述第二材料上方，具有覆盖所述凹陷侧壁的一部分和所述凹部底部的一部分的掩蔽区域，以及设置在所述凹部侧壁的相对部分上方的窗口和所述凹部底部的相对部分， 第二材料的部分。 在半导体本体的暴露的下部设置蚀刻，以在半导体本体中形成浅沟槽。 在浅沟槽中形成绝缘材料以形成浅沟槽隔离区域。 通过这种方法，允许更大的掩模未对准公差。
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公开(公告)号：EP0987765A3
公开(公告)日：2000-11-29
申请号：EP99113439.6
申请日：1999-07-10
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10861
摘要： The present invention relates to a process of fabricating semiconductor memory structures, particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor. Specifically, the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing. This process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material. Furthermore, the process of the present invention limits the extent of the buried- strap outdiffusion, thus improving the electrical characteristics of the array MOSFET.
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10.发明公开
公开(公告)号：EP1032040A3
公开(公告)日：2001-11-21
申请号：EP00103742.3
申请日：2000-02-23
IPC分类号： H01L23/525
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.
摘要翻译： 集成电路具有初级器件，并且冗余器件通过至少一个保险丝选择性地代替初级器件。 熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。
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