公开(公告)号：EP0955640A2

公开(公告)日：1999-11-10

申请号：EP99302503.0

申请日：1999-03-30

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Kiehl, Oliver ,  Parent, Richard M.

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

摘要翻译： 计算机存储器系统中的动态随机存取存储器芯片（DRAM）被制造为更可用于由处理器访问，即使当处理器试图访问存储器系统时，可能正在进行自动刷新周期。 定义了一个DECODED AUTOREFRESH模式，只允许刷新DRAM的某些存储区。 来自外部DRAM控制器的存储体地址选择必须执行AUTOREFRESH的存储区。 DRAM控制器电路确保DRAM的每个存储体都经常获得刷新命令，足以保留信息。

公开(公告)号：EP0955640A3

公开(公告)日：2000-01-19

申请号：EP99302503.0

申请日：1999-03-30

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Kiehl, Oliver ,  Parent, Richard M.

IPC分类号： G11C11/406

CPC分类号： G11C11/406

摘要： Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

公开(公告)号：EP0563852A1

公开(公告)日：1993-10-06

申请号：EP93105170.0

申请日：1993-03-29

申请人： SIEMENS AKTIENGESELLSCHAFT ,  International Business Machines Corporation

发明人： Galbi, Duane Elmer ,  Guthrie, William Hewlett ,  Kiehl, Oliver ,  Mandelman, Jack Allan ,  Watts, Josef Samuel

IPC分类号： H01L23/525

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse. The predictability of the point of fuse blow out allows even greater circuit densities while minimizing the possibility of accidental damage to adjacent devices.

摘要翻译： 具有降低的电流要求从而使驱动晶体管所需的电源电压和芯片面积最小化的保险丝具有几何形状，其特征在于在熔丝链的整个主轴上具有基本均匀的宽度尺寸，但具有至少一个约 熔断体直角弯曲。 熔断器可以吹开大约10％的输入电流密度所需的直流熔断器等截面积。 这样做的原因是，由于目前的拥挤，电流密度在弯曲的内部角落被强化。 当保险丝的输入电流增加时，在内角处达到电流密度，导致熔丝材料熔化。 内角处形成凹痕。 通过开槽改变的保险丝几何在槽口处产生更严重的电流拥挤，这又导致熔化物在保险丝的宽度上传播。 保险丝熔断点的可预测性允许更大的电路密度，同时最小化对相邻设备的意外损坏的可能性。

公开(公告)号：EP1133055A3

公开(公告)日：2004-07-21

申请号：EP01302052.4

申请日：2001-03-06

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Kiehl, Oliver ,  Houghton, Russ

IPC分类号： H03K3/3565

CPC分类号： H03K3/3565

摘要： A receiver circuit, in accordance with the present invention, includes a first stage (202) having an input for receiving input signals (VIN) and an output node (220). The first stage includes an amplifier, and a second stage (223) includes an input coupled to the output of the first stage. The second stage also includes a logic gate (224) coupled to the output of the first stage, the logic gate having an output (OUT) representing the output of the receiver circuit, and a feed back element (226) coupled from the logic gate output and connecting to a switching element (228 or 230). The switching element, being responsive to the logic gate output, switches a current source (231 or 233) on and off to adjust a switchpoint of the receiver circuit.

摘要翻译： 根据本发明的接收机电路包括具有用于接收输入信号（VIN）和输出节点（220）的输入的第一级（202）。 第一级包括放大器，第二级（223）包括耦合到第一级的输出的输入端。 第二级还包括耦合到第一级的输出的逻辑门（224），逻辑门具有表示接收器电路的输出的输出（OUT）和从逻辑门耦合的反馈元件（226） 输出并连接到开关元件（228或230）。 响应于逻辑门输出的开关元件开启和关闭电流源（231或233）以调整接收器电路的切换点。

公开(公告)号：EP1133055A2

公开(公告)日：2001-09-12

申请号：EP01302052.4

申请日：2001-03-06

申请人： Infineon Technologies North America Corp. ,  International Business Machines Corporation

发明人： Kiehl, Oliver ,  Houghton, Russ

IPC分类号： H03K3/3565

CPC分类号： H03K3/3565

摘要： A receiver circuit, in accordance with the present invention, includes a first stage (202) having an input for receiving input signals (VIN) and an output node (220). The first stage includes an amplifier, and a second stage (223) includes an input coupled to the output of the first stage. The second stage also includes a logic gate (224) coupled to the output of the first stage, the logic gate having an output (OUT) representing the output of the receiver circuit, and a feed back element (226) coupled from the logic gate output and connecting to a switching element (228 or 230). The switching element, being responsive to the logic gate output, switches a current source (231 or 233) on and off to adjust a switchpoint of the receiver circuit.

公开(公告)号：EP0905702A3

公开(公告)日：1999-09-01

申请号：EP98115969.2

申请日：1998-08-25

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Kiehl, Oliver

IPC分类号： G11C7/06

CPC分类号： G11C7/062

摘要： A sensing system for sensing data from a data source and driving a pair of output lines in response thereto comprises: a primary sensing device operatively coupled to the data source for sensing and storing said data therein; and a secondary sensing device operatively coupled to the primary sensing device via a pair of input lines and also operatively coupled to the pair of output lines, the secondary sensing device being responsive to a differential voltage generated across the pair of input lines in accordance with said data stored by the primary sensing device and the secondary sensing device having a differential voltage threshold range associated therewith defined by a negative threshold and a positive threshold, whereby the secondary sensing device drives the pair of output lines to a first output condition when the differential voltage across the pair of input lines is within the differential voltage threshold range, to a second output condition when the differential voltage is at least equal to the negative threshold, and to a third output condition when the differential voltage is at least equal to the positive threshold.

摘要翻译： 一种用于感测来自数据源的数据并且响应于此来驱动一对输出线的感测系统包括：主感测装置，其可操作地耦合到数据源用于感测并存储其中的所述数据; 以及次级感测设备，其经由一对输入线可操作地耦合到所述初级感测设备，并且还可操作地耦合到所述一对输出线，所述次级感测设备响应于根据所述一对输入线在所述一对输入线上产生的差分电压 由所述主感测装置和所述次感测装置存储的数据具有由负阈值和正阈值限定的与之相关联的差分电压阈值范围，由此当所述差分电压 在差分电压阈值范围内，在差分电压至少等于负阈值时将第一输出条件设置为第二输出条件，并且在差分电压至少等于正阈值时将第一输出条件设置为第三输出条件 。

公开(公告)号：EP0602526B1

公开(公告)日：1999-03-03

申请号：EP93119791.7

申请日：1993-12-08

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Kiehl, Oliver ,  Bonner, Fergal ,  Killian, Michael ,  Lau, Klaus J.

IPC分类号： G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

公开(公告)号：EP0602526A2

公开(公告)日：1994-06-22

申请号：EP93119791.7

申请日：1993-12-08

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Kiehl, Oliver ,  Bonner, Fergal ,  Killian, Michael ,  Lau, Klaus J.

IPC分类号： G11C7/06 ,  G11C11/409

CPC分类号： G11C7/065

摘要： A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

摘要翻译： 一种解码源极读出放大器，其中列选择信号被整形，使得它在读出放大器的源极接地之后的预定时间导通位选择晶体管，从而给读出放大器提供时间以在其之前锁存 被耦合到外部位线。

公开(公告)号：EP0668561B1

公开(公告)日：2002-04-10

申请号：EP95101257.4

申请日：1995-01-30

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Kiehl, Oliver

IPC分类号： G06F11/10

CPC分类号： G06F11/1008

摘要： A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal.

公开(公告)号：EP0907184A2

公开(公告)日：1999-04-07

申请号：EP98115819.9

申请日：1998-08-21

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： Krause, Gunnar H. ,  Kiehl, Oliver

IPC分类号： G11C29/00

CPC分类号： G11C29/28

摘要： Testing of a multibank memory device having a plurality of memory banks which includes activating two or more of the plurality of memory banks for participation in the test; selecting at least one common memory address corresponding to a memory cell within each activated bank; simultaneously writing test data into the selected memory cell of each activated bank;
simultaneously reading the test data previously written into the selected memory cell of each activated bank; and comparing the test data read from each activated bank with the test data from each other activated bank and if a match is determined to exist, then indicating a pass condition, else indicating a fail condition.

摘要翻译： 具有多个存储体的多存储器件的测试包括激活多个存储器组中的两个或更多个参与测试; 选择对应于每个激活的存储体内的存储器单元的至少一个公共存储器地址; 同时将测试数据写入每个激活的存储体的选定存储单元; 同时读取先前写入每个激活银行的选定存储单元的测试数据; 并且将从每个激活的存储体读取的测试数据与来自彼此激活的存储体的测试数据进行比较，并且如果确定存在匹配，则指示通过条件，否则指示失败状况。