公开(公告)号：EP3249414A4

公开(公告)日：2018-03-14

申请号：EP16760993

申请日：2016-01-04

申请人： STATE NUCLEAR POWER AUTOMATION SYSTEM ENG

发明人： JIANG QUNXING ,  WANG XIAOKAI ,  SI SHENGJIAN ,  PEI YUSEN ,  ZHU HUAIYU ,  YE TAO ,  ZHOU BING ,  SHI TENG

IPC分类号： G01R31/00 ,  G01R29/027 ,  G01R31/317 ,  G01R31/3185

CPC分类号： G01R31/31725 ,  G01R29/0273 ,  G01R31/31727 ,  G01R31/318519

摘要： An FPGA clock signal self-detection method relates to the technical field of control module, and the technical problem to be solved is to improve operational reliability and safety of the FPGA chip. The method comprises introducing two clock signals to an FPGA chip, wherein one clock signal is a first clock signal, and the other clock signal is a second clock signal; using the first clock signal to control all synchronous logic operations in the FPGA chip, and using the second clock signal to detect the first clock signal for correctness. The method of the invention is particularly applicable to a system with the FPGA chip as a main controller or important control unit.

公开(公告)号：EP3249543A4

公开(公告)日：2018-04-11

申请号：EP16829550

申请日：2016-01-04

申请人： STATE NUCLEAR POWER AUTOMATION SYSTEM ENG

发明人： ZHANG JIAN ,  JIANG QUNXING ,  WANG XIAOKAI

IPC分类号： G06F13/40

CPC分类号： G06F13/40

摘要： An FPGA-based interface signal remapping method, relates to the technical field of nuclear power system, and solves the technical problems of poor reliability, readability and debuggability in the prior art. The method comprises dividing an internal programmable logic of an FPGA chip into two independent modules, with one module being an I/O module and the other module being a Core module, using the I/O module to process signal excursion occurring when an external signal is input to or output from the FPGA chip, signal collision caused by line multiplexing, metastable state in a data transmission process, and a data transmission error between asynchronous clock domains, using the Core module to implement logical processing and computing; and introducing a master clock signal outside the FPGA chip into the FPGA chip through a global clock pin of the FPGA chip. The method provided in the invention is suitable for a nuclear power protection system platform.