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    Circuit and method for detecting the state of a switch
    1.
    发明公开
    Circuit and method for detecting the state of a switch 有权
    电路和方法，用于确定开关的状态

    公开(公告)号：EP1343184A3

    公开(公告)日：2006-07-05

    申请号：EP03251410.1

    申请日：2003-03-07

    Applicant: STMicroelectronics, Inc.

    Inventor： Yin, Rong ,  Youssef, Tom ,  McClure, David Charles

    IPC: H01H9/16

    CPC classification number: H01H9/167 ,  H03K17/18 ,  Y10T307/74 ,  Y10T307/766

    Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

    Circuit and method for detecting the state of a switch
    6.
    发明公开
    Circuit and method for detecting the state of a switch 有权
    Schaltung und Verfahren zur Feststellung des Zustandes eines Schalters

    公开(公告)号：EP1343184A2

    公开(公告)日：2003-09-10

    申请号：EP03251410.1

    申请日：2003-03-07

    Applicant: STMicroelectronics, Inc.

    Inventor： Yin, Rong ,  Youssef, Tom ,  McClure, David Charles

    IPC: H01H9/16

    CPC classification number: H01H9/167 ,  H03K17/18 ,  Y10T307/74 ,  Y10T307/766

    Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch. The circuit may include a first circuit for temporarily driving the second terminal of the switch to a second logic level. A second circuit, coupled to the switch, senses a voltage level of the second terminal of the switch and generates an output signal representative of the voltage sensed. A sequential logic circuit is responsive to the output signal of the second circuit so as to maintain a logic value representative of the switch having been closed.

    Abstract translation: 公开了用于检测诸如机械开关之类的开关的启动的电路和方法。 电路可以包括用于将开关的第二端子临时驱动到第二逻辑电平的第一电路。 耦合到开关的第二电路感测开关的第二端子的电压电平，并产生表示所感测的电压的输出信号。 顺序逻辑电路响应于第二电路的输出信号，以便保持表示开关已经闭合的逻辑值。

    An improved power-on reset circuit for controlling test mode entry
    9.
    发明公开
    An improved power-on reset circuit for controlling test mode entry 失效
    改进的动力，以Prüfmoduseintrittssteuerung

    公开(公告)号：EP0773552A3

    公开(公告)日：2000-04-19

    申请号：EP96113904.5

    申请日：1991-08-12

    Applicant: STMicroelectronics, Inc.

    Inventor： McClure, David Charles

    IPC: G11C29/00 ,  G01R31/318

    CPC classification number: G11C7/22 ,  G01R31/31701 ,  G06F1/24 ,  G11C29/46 ,  H03K3/0375 ,  H03K3/356008

    Abstract: An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

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