公开(公告)号：EP1220092B8

公开(公告)日：2011-09-21

申请号：EP01310645.5

申请日：2001-12-19

申请人： STMicroelectronics, Inc. ,  Hewlett-Packard Company

发明人： Jarvis, Anthony X. ,  Faraboschi, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855

公开(公告)号：EP1221648A1

公开(公告)日：2002-07-10

申请号：EP01310634.9

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Jarvis, Anthony X.

IPC分类号： G06F9/38

CPC分类号： G06F9/3013 ,  G06F9/3828 ,  G06F9/3857 ,  G06F9/3891

摘要： There is disclosed a data processor that uses bypass circuitry to transfer result data from late pipeline stages to earlier pipeline stages in an efficient manner and with a minimum amount of wiring. The data processor comprises: 1) an instruction execution pipeline comprising a) a read stage; b) a write stage; and c) a first execution stage comprising E execution units that produce data results from data operands. The data processor also comprises: 2) a register file comprising a plurality of data registers, each of the data registers being read by the read stage of the instruction pipeline via at least one of R read ports of the register file and each of the data registers being written by the write stage of the instruction pipeline via at least one of W write ports of the register file; and 3) bypass circuitry for receiving data results from output channels of source devices in at least one of the write stage and the first execution stage, the bypass circuitry comprising a first plurality of bypass tristate line drivers having input channels coupled to first output channels of a first plurality of source devices and tristate output channels coupled to a first common read data channel in the read stage.

摘要翻译： 公开了一种数据处理器，其使用旁路电路以有效的方式并且以最少量的布线将结果数据从晚期流水线级传送到较早的流水线级。 数据处理器包括：1）指令执行流水线，其包括a）读阶段; b）写阶段; 以及c）第一执行阶段，其包括从数据操作数产生数据结果的E个执行单元。 数据处理器还包括：2）包括多个数据寄存器的寄存器文件，每个数据寄存器由指令流水线的读取级通过寄存器堆的R个读出端口和每个数据中的至少一个读取 寄存器通过寄存器堆的W个写入端口中的至少一个写入指令流水线的写入级; 以及3）旁路电路，用于从写入级和第一执行级中的至少一个中的源器件的输出通道接收数据结果，旁路电路包括第一多个旁路三态线驱动器，其具有耦合到第一输出通道的输入通道 耦合到读取级中的第一公共读取数据信道的第一多个源设备和三态输出通道。

公开(公告)号：EP1220091B1

公开(公告)日：2009-08-05

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

公开(公告)号：EP1220091A3

公开(公告)日：2002-12-04

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

摘要： There is disclosed bundle alignment and dispersal circuitry for use in a data processor. The data processor comprises: 1) C execution clusters, each of the C execution clusters comprising an instruction execution pipeline having N processing stages for executing instruction bundles comprising from one to S syllables, wherein each the instruction execution pipelines is L lanes wide, each of the L lanes for receiving one of the one to S syllables of the instruction bundles; 2) an instruction cache for storing a plurality of cache lines, each of the cache lines comprising C*L syllables; 3) an instruction issue unit for receiving fetched ones of the plurality of cache lines and issuing complete instruction bundles toward the C execution clusters; and 4) alignment and dispersal circuitry for receiving the complete instruction bundles from the instruction issue unit and routing each the received complete instruction bundles to a correct one of the C execution clusters as a function of at least one address bit associated with each of the complete instruction bundles.

摘要翻译： 公开了用于数据处理器的束对准和分散电路。 数据处理器包括：1）C个执行群集，每个C个执行群集包括具有N个处理阶段的指令执行流水线，用于执行包括从1到S个音节的指令包，其中每个指令执行流水线是L个通道宽度， 用于接收指令集的一个到S个音节中的一个的L个通道; 2）用于存储多个高速缓存行的指令高速缓存，每个高速缓存行包括C * L音节; 3）指令发布单元，用于接收所述多个高速缓存行中的获取的高速缓存行，并向所述C个执行集群发布完整的指令集; 以及4）对准和分散电路，用于接收来自指令发布单元的完整指令集并且根据与每个完整指令集相关联的至少一个地址位将每个接收到的完整指令集路由到C个执行集群中的正确的一个C执行集群 指令包。

公开(公告)号：EP1220092A2

公开(公告)日：2002-07-03

申请号：EP01310645.5

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Jarvis, Anthony X. ,  Faraboschi, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855

摘要： There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages for performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of registers for receiving the data values from the data cache; 4) a load store unit for transferring a first one of the data values from the data cache to a target one of the plurality of registers during execution of a load operation; 5) a shifter circuit associated with the load store unit for shifting the first data value prior to loading the first data value into the target register; and 6) bypass circuitry associated with the load store unit for transferring the first data value from the data cache directly to the target register without processing the first data value in the shifter circuit.

摘要翻译： 公开了一种数据处理器，其使用旁路电路执行可变等待时间负载操作，其允许负载字操作以避免由移位电路引起的停顿。 所述处理器包括：1）包括N个处理级的指令执行流水线，所述N个处理级中的每一个用于执行与由所述指令执行管线执行的待决指令相关联的多个执行步骤之一; 2）用于存储待决指令使用的数据值的数据高速缓存; 3）多个用于从数据高速缓存接收数据值的寄存器; 4）一种加载存储单元，用于在执行加载操作期间将数据值中的第一个数据值从数据高速缓存传送到多个寄存器中的目标寄存器; 5）与加载存储单元相关联的移位器电路，用于在将第一数据值加载到目标寄存器之前移位第一数据值; 和6）与加载存储单元相关联的旁路电路，用于将第一数据值从数据高速缓存直接传送到目标寄存器，而不处理移位器电路中的第一数据值。

公开(公告)号：EP1220092B1

公开(公告)日：2011-06-15

申请号：EP01310645.5

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Jarvis, Anthony X. ,  Faraboschi, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855

公开(公告)号：EP1221648B1

公开(公告)日：2007-03-28

申请号：EP01310634.9

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Jarvis, Anthony X.

IPC分类号： G06F9/38

CPC分类号： G06F9/3013 ,  G06F9/3828 ,  G06F9/3857 ,  G06F9/3891

公开(公告)号：EP1220092A3

公开(公告)日：2006-04-26

申请号：EP01310645.5

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Jarvis, Anthony X. ,  Faraboschi, Paolo

IPC分类号： G06F9/38

CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3885 ,  G06F9/3891 ,  G06F12/0855

摘要： There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N processing stages, each of the N processing stages for performing one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; 2) a data cache for storing data values used by the pending instruction; 3) a plurality of registers for receiving the data values from the data cache; 4) a load store unit for transferring a first one of the data values from the data cache to a target one of the plurality of registers during execution of a load operation; 5) a shifter circuit associated with the load store unit for shifting the first data value prior to loading the first data value into the target register; and 6) bypass circuitry associated with the load store unit for transferring the first data value from the data cache directly to the target register without processing the first data value in the shifter circuit.

公开(公告)号：EP1220091A2

公开(公告)日：2002-07-03

申请号：EP01310630.7

申请日：2001-12-19

申请人： STMicroelectronics, Inc.

发明人： Faraboschi, Paolo ,  Jarvis, Anthony X. ,  Homewood, Mark Owen

IPC分类号： G06F9/38

CPC分类号： G06F9/3891 ,  G06F9/30054 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/3853 ,  G06F9/3885

摘要： There is disclosed bundle alignment and dispersal circuitry for use in a data processor. The data processor comprises: 1) C execution clusters, each of the C execution clusters comprising an instruction execution pipeline having N processing stages for executing instruction bundles comprising from one to S syllables, wherein each the instruction execution pipelines is L lanes wide, each of the L lanes for receiving one of the one to S syllables of the instruction bundles; 2) an instruction cache for storing a plurality of cache lines, each of the cache lines comprising C*L syllables; 3) an instruction issue unit for receiving fetched ones of the plurality of cache lines and issuing complete instruction bundles toward the C execution clusters; and 4) alignment and dispersal circuitry for receiving the complete instruction bundles from the instruction issue unit and routing each the received complete instruction bundles to a correct one of the C execution clusters as a function of at least one address bit associated with each of the complete instruction bundles.

摘要翻译： 公开了用于数据处理器的捆绑对齐和分散电路。 数据处理器包括：1）C个执行群集，每个C执行群包括一个指令执行流水线，该指令执行流水线具有N个处理级，用于执行包括从一个到S个音节的指令束，其中每个指令执行管线是L通道， 用于接收指令束中的一个到S个音节的L通道; 2）用于存储多个高速缓存行的指令高速缓存，每个高速缓存行包括C * L个音节; 3）指令发布单元，用于接收所述多个高速缓存行中的取出的数据，并向所述C个执行簇发出完整指令束; 以及4）对准和分散电路，用于从指令发布单元接收完整的指令束，并将所接收的完整指令束中的每一个作为与所述完整指令中的每一个相关联的至少一个地址位的函数， 指令包。