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公开(公告)号：EP1667158B1
公开(公告)日：2007-01-31
申请号：EP04105354.7
申请日：2004-10-28
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公开(公告)号：EP4261651A1
公开(公告)日：2023-10-18
申请号：EP23305469.1
申请日：2023-03-31
发明人： CONTE, Antonino , RUTA, Marco , TOMAIUOLO, Francesco , PISASALE, Michelangelo , GRIMAL, Marion Helne
IPC分类号： G05F1/56
摘要： A LDO regulator circuit comprises an input comparator (10) as well as driver circuitry including transistors (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) having a current flow path therethrough coupled to an output node (vout) of the regulator. A first (12A) and a second (12B) driver each comprises: driver transistors (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) having the current flow paths therethrough coupled to the output node (vout), capacitive boost circuitry (C1A, C1B, C2A, C2B) that applies to the drive transistors (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) a voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP _OUT). Voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) coupled to the capacitive boost circuitry (C1A, C1B, C2A, C2B) transfer thereon the voltage-pumped (100A, vbl_boost) replica of the comparison signal (COMP_OUT). The first (12A) and second (12B) drivers can be controllably (PA_LV, PB_LV) switched between:
a first mode of operation, during which the current flow path through the driver transistors (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is conductive or non-conductive based on the voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP_OUT), and
a second mode of operation, during which the voltage refresh transistor circuitry (M1A, M2A, M1B, M2B) coupled to the voltage boost capacitive circuitry (C1A, C1B, C2A, C2B) is activated (ON) to transfer thereon the voltage-pumped (100A; vbl_boost) replica of the comparison signal (COMP_OUT), and the current flow path through the driver transistors (MDRV_1A, MCASC_2A, MDRV_1B, MCASC_2B) is non-conductive.-
3.发明公开
公开(公告)号：EP4123651A1
公开(公告)日：2023-01-25
申请号：EP22181479.1
申请日：2022-06-28
发明人： MACCARRONE, Agatino Massimo , CONTE, Antonino , TOMAIUOLO, Francesco , PISASALE, Michelangelo , RUTA, Marco
IPC分类号： G11C13/00
摘要： A circuit comprises a plurality of memory cells (C1, ..., CN). Each memory cell in the plurality of memory cells (C1, ..., CN) includes a phase-change memory storage element (E1) coupled in series with a respective current-modulating transistor (PH1) between a supply voltage node (V SUPPLY ) and a reference voltage node. The current-modulating transistors (PH1) are configured to receive a drive signal (DRV _GATE) at a control terminal thereof and to inject respective programming currents (I CELL ) into the respective phase-change memory storage elements (E1) as a function of the drive signal (DRV_GATE). A driver circuit (32) is configured to produce the drive signal (DRV _GATE) at a common control node (N C ), and the common control node (N C ) is coupled to the control terminals of the current-modulating transistors (PH1) in the plurality of memory cells (C1, ..., CN). The drive signal (DRV _GATE) modulates the programming currents (I CELL ) to produce set programming current pulses and reset programming current pulses. A current generator circuit (80) is configured to inject a compensation current (I DRV_GATE ) into the common control node (N C ) in response to the current-modulating transistors (PH1) injecting the programming currents (I CELL ) into the respective phase-change memory storage elements (E1).
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4.发明公开A voltage down-converter with reduced ripple 有权Spannungs-Abwärts-Wandler mit reduzierter Welligkeit
公开(公告)号：EP1667158A1
公开(公告)日：2006-06-07
申请号：EP04105354.7
申请日：2004-10-28
摘要： A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.
摘要翻译： 提出了用于提供低于转换器的电源电压（Vdd）的输出电压（Vo）的降压转换器（125）。 转换器包括电压调节装置（205），用于通过利用控制信号（Vg）控制可变电导率元件（Tr）来获得与来自电源电压的输出电压相对应的中间电压（Vr） 用于通过控制另外的可变电导率元件（Tsb，T 1 -TN）来获得来自电源电压的输出电压的输出级（220,225×1〜225N）的中间电压（Vr）和参考电压（Vbg） 与所述控制信号相关联，其中所述另一可变导电元件具有至少一个多个基本模块（225 1至225 N）的组（MM，ML，MH）的模块化结构，所述转换器还包括装置（230，SW 1 - SW N），用于根据输出电压和中间电压之间的比较来连续地启用和/或禁用每组的模块。
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公开(公告)号：EP4262090A1
公开(公告)日：2023-10-18
申请号：EP23305468.3
申请日：2023-03-31
IPC分类号： H03K19/0185 , H03K3/356
摘要： A level-shifter circuit (10) receives one or more input signals (IN; LS) in an input level domain and provides at an output node an output signal (OUT; OUT_S) in an output level domain shifted with respect to the input level domain. The circuit (10) comprises output circuitry (MPA, MPB, MP CASC , MN CASC , MNO) including a first drive node (A) and a second drive node (B) that receive first (PhaseACond) and second (PhaseBCond) logical signals so that the output signal (OUT) has a first output level or a second output level in the output level domain as a function of at least one of the first and second logical signals (PhaseACond, PhaseBCond). The circuit comprises first (C SHIFTL ) and second (C SHIFTR ) shift capacitors coupled to the first (A) and second (B) drive nodes as well as capacitor refresh circuitry comprising a first, resp. second, refresh transistor (MPS_A resp. MPS_B) with first, resp. second refresh current flow paths therethrough between a supply node (VX) and the first (C SHIFTL ) resp. second (C SHIFTR ) shift capacitor via the first (A) resp. second (B) drive node. The refresh current flow paths are configured to become conductive in response to a respective refresh signal (PhaseA_S, resp. PhaseB_S) applied to the control terminal of the respective refresh transistor (MPS_A, resp. MPS_B) as well as logic circuitry (100A, 100B) configured to facilitate charge of the shift capacitors (C SHIFTL resp. C SHIFTR ) via the refresh current flow paths in response to shifted refresh signals (PhaseALV; PhaseBLV) that are shifted with respect to the refresh signals (PhaseA_S resp. PhaseB_S) applied to the control terminal of the respective refresh transistor (MPS_A, resp. MPS_B).
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公开(公告)号：EP4174859A1
公开(公告)日：2023-05-03
申请号：EP22192488.9
申请日：2022-08-26
发明人： RUTA, Marco , CONTE, Antonino , PISASALE, Michelangelo , MACCARRONE, Agatino Massimo , TOMAIUOLO, Francesco
摘要： A low-dropout voltage regulator circuit (40) is disclosed. The regulator receives an input voltage ( Vcc ) at an input node (400) and produces a regulated output voltage ( V REG ) at an output node (402). A first feedback network (R1, 412, 414) produces a feedback signal ( VFB ) indicative of the output voltage ( V REG ), and compares the feedback signal to a reference signal ( VREF ) to assert and de-assert a first pulsed control signal ( COMP_OU-T ) when the reference signal is higher and lower, respectively, than the feedback signal. A time-averaged value of the first pulsed control signal is a function of the difference between the reference signal and the feedback signal. A second feedback network (R2, 418, 420) produces a threshold signal ( VTH ) indicative of the input voltage, and compares the output voltage ( V REG ) to the threshold signal to assert and de-assert a second control signal ( VCC_EN ) when the threshold signal is higher and lower, respectively, than the output voltage. A charge pump circuit (408) is enabled ( PMP_EN ) if the second control signal is de-asserted and is clocked by the first pulsed control signal to produce a supply voltage ( V BL_ S UPPLY ) higher than the input voltage ( Vcc ) . A first pass element (404a) arranged between the input node and the output node is enabled when the second control signal is asserted and is selectively activated when the first pulsed control signal is asserted. A second pass element (404b) arranged between the charge pump (408) and the output node (402) is selectively activated when the second control signal is de-asserted.
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公开(公告)号：EP4106191A1
公开(公告)日：2022-12-21
申请号：EP22305799.3
申请日：2022-06-01
摘要： A ring oscillator (50) comprises a chain of inverters (52) coupled between an oscillator supply node (54) and a reference node (56), and a current generator (58) coupled between the oscillator supply node and a system supply node (60) and configured to inject a current (I OSC ) into the oscillator supply node. Each inverter comprises a first (N F ) and a second (N L ) low-side transistors coupled in series between the reference node and an output node of the inverter, and a first high-side transistor (P F1 ) coupled between the oscillator supply node and the output node of the inverter. The first low-side transistor and the first high-side transistor have respective control terminals coupled to an input node of the inverter to receive a respective inverter control signal (CK). The second low-side transistor has a control terminal coupled to the oscillator supply node. The ring oscillator circuit further comprises a biasing circuit (500) including a first bias transistor (N FZ ) and a second bias transistor (N LZ ) coupled in series between the reference node and the oscillator supply node. The first bias transistor has a control terminal configured to receive an oscillator control signal (StartP) indicative of whether the ring oscillator is in an active or inactive operation state. The second bias transistor has a control terminal coupled to the oscillator supply node. The first bias transistor is configured to selectively couple the reference node and the oscillator supply node in response to the ring oscillator being in an inactive operation state.
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