公开(公告)号：EP4138343A1

公开(公告)日：2023-02-22

申请号：EP22188198.0

申请日：2022-08-02

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： RENNIG, Fred ,  DVORAK, Vaclav

IPC分类号： H04L12/40

摘要： A processing system (10a) is described. The processing system (10a) comprises a transmission terminal (TX) configured to provide a transmission signal (TXD), a reception terminal (RX) configured to receive a reception signal (RXD), a microprocessor (1020) programmable via software instructions, a memory controller (100) configured to be connected to a memory (104, 104b), a serial communication interface (50), and a communication system (114).
Specifically, the serial communication interface (50) supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface (50) comprises a control register (CTRL), a clock management circuit (5044), a transmission shift register (5040; 5056), a transmission control circuit (5046), a reception shift register (5042; 5056) and a reception control circuit (5048).
Accordingly, the microprocessor (1020) may transmit and/or receive CAN FD Light or UART frames via the same serial communication interface (50).

公开(公告)号：EP4246900A1

公开(公告)日：2023-09-20

申请号：EP23158838.5

申请日：2023-02-27

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o. ,  STMicroelectronics S.r.l.

发明人： RENNIG, Fred ,  BARTHEL, Jochen ,  BERAN, Ludek ,  DONDINI, Mirko ,  DVORAK, Vaclav ,  POLISI, Vincenzo ,  SANZA', Marianna ,  TRECARICHI, Calogero Andrea ,  FURIO, Alfonso

IPC分类号： H04L12/40 ,  G06F13/40 ,  G06F13/42

摘要： A processing system (10a) is described. The processing system comprises a three-state driver circuit (502) and a CAN FD Light controller (500). The CAN FD Light controller (500) is configured to sequentially transmit the bits of a CAN FD Light frame, wherein the CAN FD Light frame comprises a start-of-frame bit (SOF), a sequence of bits (CD-EOF) comprising in sequence a Cyclic Redundancy Check, CRC, delimiter bit (CD), an acknowledge bit (AS), an acknowledge delimiter bit (AD) and an End-of-Frame field (EOF) having 7 bits, and a plurality of intermediate bits (SID-CRC) between said start-of-frame bit (SOF) and said CRC delimiter bit (CD).
In particular, the CAN FD Light controller (500) is configured to sequentially transmit the bits of the CAN FD Light frame via the three-state driver circuit (502) by using a push-pull configuration (CTRL1) when transmitting the start-of-frame bit (SOF) and the intermediate bits (SID-CRC). However, once having transmitted the intermediate bits (SID-CRC), the CAN FD Light controller (500) activates a high-impedance state (CTRL1) of the three-state driver circuit (502).

公开(公告)号：EP3913864A1

公开(公告)日：2021-11-24

申请号：EP21172208.7

申请日：2021-05-05

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： RENNIG, Fred ,  DVORAK, Vaclav ,  BERAN, Ludek

IPC分类号： H04L12/40

摘要： A method of operating a CAN bus comprises coupling a first device (10) and second devices (20 1 , ..., 20 n ) to the CAN bus (30) via respective CAN transceiver circuits. The method comprises configuring the first device as a communication master device to transmit first messages carrying operation data message portions indicative of operations for implementation by the second devices, and second messages addressed to the second devices, the second messages conveying identifiers identifying respective ones of the second devices to which the second messages are addressed requesting respective reactions towards the first device within respective expected reaction intervals. The method comprises configuring the second devices as communication slave devices to receive the first messages transmitted from the first device, read respective operation data message portions in said operation data message portions and implement respective operations as a function of the respective operation data message portions read, and to receive the second messages transmitted from the first device and react thereon within said respective expected reaction intervals by transmitting reaction messages towards the first device. The method comprises configuring said respective CAN transceiver circuits to set the CAN bus to a recessive level during transmission of said messages via the CAN bus by the respective first device or second device.

公开(公告)号：EP4137954A1

公开(公告)日：2023-02-22

申请号：EP22188131.1

申请日：2022-08-01

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： DVORAK, Vaclav ,  RENNIG, Fred

IPC分类号： G06F13/42 ,  G06F12/0806 ,  G06F13/40 ,  H04L12/40 ,  G06F13/28 ,  G06F13/38

摘要： A processing system (10a) is described. The processing system comprises a Serial Peripheral Interface, SPI, communication interface (50), a microprocessor (1020), a memory controller (100) connected to a memory (104, 104b), and two DMA channels (DMA 1 , DMA 2 ) configured to transfer packets between the SPI interface (50) and the memory (104b). In particular, the processing system comprises an edge detector (600, 620) configured to assert a first control signal (IRQ 60 ) in response to a falling edge in the reception signal (RXD), a first hardware timer circuit (60) configure to, when enabled, generate a clock signal (PWM) for the SPI communication interface (50) and a second hardware timer circuit (62) configure to, when enabled, increase a count value and assert a second control signal (IRQ 62 ) in response to determining that the count value reaches a given threshold value.
Specifically, the processing system (10a) is configured to manage a CAN FD Light data transmission mode and/or CAN FD Light data reception mode by using the SPI communication interface. For example, in the CAN FD Light data reception mode, the microprocessor (1020) activates a slave mode of the SPI communication interface (50), enables the first hardware timer circuit (60) and the second hardware timer circuit (62) in response to the first control signal (IRQ 60 ), whereby the second DMA channel (DMA 2 ) transfers packets from the SPI communication interface (50) to the memory (104b), thereby sequentially transferring a reception CAN FD Light frame from the SPI communication interface (50) to the memory (104b), and reads the reception CAN FD Light frame from the memory (104b) in response to the second control signal (IRQ 62 ).

公开(公告)号：EP4057574A1

公开(公告)日：2022-09-14

申请号：EP22157917.0

申请日：2022-02-22

申请人： STMicroelectronics Application GmbH ,  STMicroelectronics Design and Application s.r.o.

发明人： RENNIG, Fred ,  DVORAK, Vaclav

IPC分类号： H04L12/40 ,  H03K7/08

摘要： A circuit (106) comprises a first (24a) and a second (24b) memory, a processing unit (21) and a timer (22). The processing unit generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. Each PWM period has a dominant portion and a recessive portion, and a total duration. The processing unit stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory, wherein the first and second parameter define a shape of the PWM periods. The timer comprises a first register (220) which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter (221) which increases a count number and resets the count number as a function of the value of the first register. A value of the first parameter of a subsequent PWM period is stored into the first register as a function of the value of the first register. The timer comprises a second register (222) which reads from the second memory a value of the second parameter of the current PWM period, and compares the count number of the counter circuit to such value. The second register drives an output pin (230) to a dominant (resp., recessive) value as a function of said comparing the count number of the counter circuit to the value of the second register. A value of the second parameter of a subsequent PWM period is stored into the second register in response to the count number reaching the value stored in the first or second register.