公开(公告)号：EP3038109B1

公开(公告)日：2018-04-11

申请号：EP15187696.8

申请日：2015-09-30

申请人： STMicroelectronics International N.V.

发明人： Rawat, Harsh ,  JAIN, PIYUSH

IPC分类号： G11C8/16 ,  G11C7/10 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

摘要： A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

公开(公告)号：EP3038109A1

公开(公告)日：2016-06-29

申请号：EP15187696.8

申请日：2015-09-30

申请人： STMicroelectronics International N.V.

发明人： Rawat, Harsh ,  JAIN, PIYUSH

IPC分类号： G11C8/16 ,  G11C7/10 ,  G11C11/419 ,  G11C11/418

CPC分类号： G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

摘要： A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

摘要翻译： 伪双端口存储器包括一组具有一个读端口和一个写端口的双端口存储器单元，并且在每个寻址位置的多个被配置为存储数据字，并具有读一组单端口存储器单元的/写 端口，和被配置为存储在每个寻址位置的多个数据字。 一个有效的数据存储单元被配置为存储有效位对应给组双端口存储器单元和所述一组单端口存储器单元的位置。 控制电路被配置成访问所述组双端口存储器单元和所述一组单端口存储器单元的被寻址的位置。 所述控制电路使用所述一组双端口存储器单元和所述一组单端口存储器单元的读/写端口的写端口执行同时写入操作，而在有效数据存储单元对应的有效比特的更新，并执行 并行读出手术，在所述一组双端口存储器单元和所述一组单端口存储器单元中的一个相同的寻址位置，使用所设置的双端口存储器单元的读取端口和该组单个端口的读/写端口 存储单元，和确定性采矿哪个存储的数据字是有效的基于所述的有效数据存储单元中的对应的有效比特。