公开(公告)号：EP2966780A1

公开(公告)日：2016-01-13

申请号：EP14306111.7

申请日：2014-07-07

申请人： STMicroelectronics International N.V.

发明人： Vaccariello, Laurent

IPC分类号： H03M1/06 ,  H03M1/40

CPC分类号： H03M1/0663 ,  H03M1/0682 ,  H03M1/0695 ,  H03M1/403

摘要： There is described a cyclic pipelined Analog-to-Digital Converter having an input (41) adapted to receive an analog voltage (V IN ) to be converted, and an output (42) adapted to deliver a n-bit digital value (N OUT ). The converter also comprises a core stage (40) comprising an Analog-to-Digital Conversion stage (50) to provide at least one bit value of the n-bit digital value at each one of a plurality of successive conversion steps performed in loop by the core stage (40). The core stage (40) further comprises a differential inputs-differential outputs amplifier (59). In order to cancel the offset of the stage (55, 58), the coupling of the amplifier inputs is inversed, i.e. the inputs are switched around, namely swapped, just after the first conversion step has been carried out. Simultaneously the differential outputs of the amplifier are similarly swapped.

摘要翻译： 描述了具有适于接收要转换的模拟电压（V IN）的输入端（41）的循环流水线模数转换器和适于传送n位数字值（N OUT）的输出（42） ）。 转换器还包括核心级（40），其包括模数转换级（50），以在循环中以循环执行的多个连续转换步骤中的每一个提供n位数字值的至少一个位值 核心阶段（40）。 核心级（40）还包括差分输入差分输出放大器（59）。 为了消除级（55,58）的偏移，放大器输入的耦合被反转，即刚刚在执行第一转换步骤之后，输入被切换，即交换。 同时，放大器的差分输出也同样交换。