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公开(公告)号：EP3836144A1
公开(公告)日：2021-06-16
申请号：EP20212102.6
申请日：2020-12-07
发明人： CHAWLA, Nitin , GROVER, Anuj , DESOLI, Giuseppe , DHORI, Kedar Janardan , BOESCH, Thomas , KUMAR, Promod
IPC分类号： G11C11/417 , G11C5/14
摘要： Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：EP4307303A3
公开(公告)日：2024-04-24
申请号：EP23174860.9
申请日：2023-05-23
IPC分类号： G11C7/10 , G06N3/063 , G11C11/419 , G11C5/14 , G11C11/418
CPC分类号： G11C7/1006 , G11C11/419 , G06N3/063 , G11C5/147 , G11C7/04 , G11C8/08 , G11C11/418
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bias voltage for word line driver and a configuration of the current mirroring circuit to inhibit drop of a voltage on the bit line below a bit flip voltage during execution of the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
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公开(公告)号：EP4307304A3
公开(公告)日：2024-04-17
申请号：EP23174861.7
申请日：2023-05-23
IPC分类号： G11C7/10 , G06N3/063 , G11C11/419 , G11C5/14 , G11C11/418
CPC分类号： G11C7/1006 , G11C11/419 , G06N3/063 , G11C11/418 , G11C5/147 , G11C8/08 , G11C7/04
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
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公开(公告)号：EP4116976A1
公开(公告)日：2023-01-11
申请号：EP22183496.3
申请日：2022-07-07
IPC分类号： G11C7/04 , G11C7/10 , G11C7/12 , G11C11/419 , G11C7/06
摘要： A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
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公开(公告)号：EP4307304A2
公开(公告)日：2024-01-17
申请号：EP23174861.7
申请日：2023-05-23
IPC分类号： G11C7/10 , G06N3/063 , G11C11/419
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit includes a clamping circuit that clamps a voltage on the bit line to a level exceeding an SRAM cell bit flip voltage during execution of the in-memory compute operation. The column processing circuit may further include a current mirroring circuit that mirrors the read current developed on each bit line in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. The mirrored read current is integrated by an integration capacitor to generate an output voltage that is converted to a digital signal by an analog-to-digital converter circuit.
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公开(公告)号：EP4300496A1
公开(公告)日：2024-01-03
申请号：EP23174864.1
申请日：2023-05-23
摘要： An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.
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公开(公告)号：EP4116974A1
公开(公告)日：2023-01-11
申请号：EP22182464.2
申请日：2022-07-01
IPC分类号： G11C5/00 , G11C7/04 , G11C11/412 , G11C11/419 , G11C7/10
摘要： An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.
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8.发明公开
公开(公告)号：EP4293671A1
公开(公告)日：2023-12-20
申请号：EP23174857.5
申请日：2023-05-23
摘要： An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.
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公开(公告)号：EP4160598A1
公开(公告)日：2023-04-05
申请号：EP22199291.0
申请日：2022-09-30
IPC分类号： G11C7/10 , G06N3/063 , G11C11/412 , G11C11/54
摘要： A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.
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公开(公告)号：EP4116977A1
公开(公告)日：2023-01-11
申请号：EP22182472.5
申请日：2022-07-01
IPC分类号： G11C7/10 , G11C7/12 , G11C11/418 , G11C11/419 , G11C8/08
摘要： A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line precharge circuit generates a precharge voltage for application to each pair of bit lines. The precharge voltage has a second voltage level (not greater than a positive supply voltage for the SRAM cells) when the memory array is operating in a data read/write mode. The precharge voltage has a first voltage level (greater than the second voltage level) in advance of the simultaneous actuation of the word lines for the in-memory compute operation.
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