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13 条记录 (耗时 0.011 秒)

    A memory device
    1.
    发明公开
    A memory device 有权
    存储设备

    公开(公告)号：EP1306852A2

    公开(公告)日：2003-05-02

    申请号：EP02078984.8

    申请日：2002-09-27

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC分类号： G11C11/34

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    摘要： A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    摘要翻译： 一种存储器件（100），包括多个存储器单元（Mh，k），在半导体材料（203）的芯片中形成的具有第一导电类型的多个绝缘第一区域（220h），至少一个第二区域 在每个第一区域中形成的第二导电类型的第二区域，每个第二区域和对应的第一区域之间的接点限定单向导通入元件（D h，k），用于当正向偏置时选择连接到第二区域的相应存储单元 以及用于接触每个第一区域的至少一个触点（225h） 在每个第一区域中形成多个存取元件，所述存取元件在不插入任何接触的情况下被分组成至少一个由多个相邻存取元件（Dh，k，Dh，k + 1）组成的子集，以及 该存储设备还包括用于同时正向偏置每个子集的访问元件的装置（110c，113,125）。

    Array of cells including a selection bipolar transistor and fabrication method thereof
    2.
    发明公开
    Array of cells including a selection bipolar transistor and fabrication method thereof 有权
    Zellenanordnung mit Bipolar-Auswahl-Transistor和Herstellungsverfahren

    公开(公告)号：EP1408550A1

    公开(公告)日：2004-04-14

    申请号：EP02425605.9

    申请日：2002-10-08

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Pellizzer, Fabio ,  Casagrande, Giulio ,  Bez, Roberto

    IPC分类号： H01L27/10 ,  H01L29/68 ,  H01L45/00

    CPC分类号： H01L27/2445 ,  H01L27/101 ,  H01L27/2463 ,  H01L29/685 ,  H01L45/06 ,  H01L45/1233

    摘要： A cell array (1) is formed by a plurality of cells (2) including each a selection bipolar transistor (4) and a storage component (3). The cell array is formed in a body (10) including a common collector region (11) of P type; a plurality of base regions (12) of N type, overlying the common collector region (11); a plurality of emitter regions (14) of P type formed in the base regions; and a plurality of base contact regions (15) of N type and a higher doping level than the base regions, formed in the base regions (12; 42), wherein each base region (12) is shared by at least two adjacent bipolar transistors (20).

    摘要翻译： 电池阵列包括设置在主体（10）中的P型公共集电极区域（11）上的N型基极区域（12）的数量。 在基极区域中形成P型发射极区域（14）和N型基极接触区域（15），使得基极接触区域的掺杂水平高于基极区域的掺杂水平，并且每个基极区域由 至少两个双极晶体管（20）。 电池阵列制造过程中还包括独立权利要求。

    Writing circuit for a phase change memory device
    5.
    发明公开
    Writing circuit for a phase change memory device 有权
    SchreibschaltungfürPhasenwechsel-Speicher

    公开(公告)号：EP1489622A1

    公开(公告)日：2004-12-22

    申请号：EP03425390.6

    申请日：2003-06-16

    申请人： STMicroelectronics S.r.l.

    发明人： Resta, Claudio ,  Bedeschi, Ferdinando ,  Pellizzer, Fabio ,  Casagrande, Giulio

    IPC分类号： G11C11/34

    CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A memory device (20) of a phase change type, wherein a memory cell (2) has a memory element (3) of calcogenic material switcheable between at least two phases associated with two different states of the memory cell. A write stage (24) is connected to the memory cell and has a capacitive circuit (35) configured to generate a discharge current used as write current having no constant portion and causing the memory cell (2) to change state.

    摘要翻译： 一种相变型存储器件（20），其中存储单元（2）具有可在存储单元的两种不同状态相关联的至少两相之间切换的钙质材料的存储元件（3）。 写入级（24）连接到存储单元，并具有电容电路（35），其被配置为产生用作不具有常数部分的写入电流的放电电流，并使存储器单元（2）改变状态。

    A memory device
    8.
    发明公开
    A memory device 有权

    公开(公告)号：EP1306852A3

    公开(公告)日：2004-03-10

    申请号：EP02078984.8

    申请日：2002-09-27

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Lowrey, Tyler ,  Bez, Roberto ,  Wicker, Guy ,  Spall, Edward ,  Hudgens, Stephen ,  Czubatyj, Wolodymyr

    IPC分类号： G11C11/34 ,  G11C16/02

    CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/72

    摘要： A memory device (100) including a plurality of memory cells (M h,k ), a plurality of insulated first regions (220 h ) of a first type of conductivity formed in a chip of semiconductor material (203), at least one second region (230 k ) of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element (D h,k ) for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact (225 h ) for contacting each first region; a plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements (D h,k ,D h,k+1 ) without interposition of any contact, and the memory device further includes means (110c,113,125) for forward biasing the access elements of each sub-set simultaneously.

    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof
    9.
    发明公开
    Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof 有权
    亚光刻接触结构，具有优化的加热结构相变存储单元，以及它们的制备方法

    公开(公告)号：EP1339103A1

    公开(公告)日：2003-08-27

    申请号：EP02425088.8

    申请日：2002-02-20

    申请人： STMicroelectronics S.r.l. ,  OVONYX Inc.

    发明人： Casagrande, Giulio ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1691

    摘要： An electronic semiconductor device has a sublithographic contact area (45, 58) between a first conductive region (22) and a second conductive region (38). The first conductive region (22) is cup-shaped and has vertical walls which extend, in top plan view, along a closed line of elongated shape. One of the walls of the first conductive region forms a first thin portion and has a first dimension in a first direction. The second conductive region (38) has a second thin portion (38a) having a second sublithographic dimension in a second direction (X) transverse to the first dimension. The first and the second conductive regions are in direct electrical contact at their thin portions and form the sublithographic contact area (45, 58). The elongated shape is chosen between rectangular and oval elongated in the first direction. Thereby, the dimensions of the contact area remain approximately constant even in presence of a small misalignment between the masks defining the conductive regions.

    摘要翻译： 一种电子半导体器件具有第一导电区（22）和一个第二导电区（38）之间的亚光刻的接触面积（45，58）。 第一导电区（22）是杯形，并具有垂直壁延伸，在俯视图中，沿着细长形状的封闭线。 一个第一导电区域的壁的形成第一薄壁部，并且具有在第一方向上的第一尺寸。 第二导电区域（38）具有在第二方向上的第二亚光刻尺寸（X）横向于第一尺寸的第二薄壁部（38A）。 所述第一和第二导电区域在其薄的部分直接电接触，并形成亚光刻接触区域（45，58）。 细长形状在第一方向上的矩形和椭圆形的细长之间选择。 因此，接触区域的尺寸，即使在掩模之间的小的未对准的存在保持大致恒定，限定导电区域。

    Ferroelectric memory cell and corresponding manufacturing method
    10.
    发明公开
    Ferroelectric memory cell and corresponding manufacturing method 审中-公开
    Ferroelektrische Speicherzelle und deren Herstellungsverfahren

    公开(公告)号：EP1067605A1

    公开(公告)日：2001-01-10

    申请号：EP99830431.5

    申请日：1999-07-05

    申请人： STMicroelectronics S.r.l.

    发明人： Casagrande, Giulio ,  Zambrano, Raffaele

    IPC分类号： H01L27/115 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/11507

    摘要： A memory cell (2) integrated in a semiconductor substrate (3) and comprised of a MOS device (4) connected in series to a capacitive element (5), wherein

    the MOS device (4) has first and second conduction terminals (6),
    the capacitive element (5) has a lower electrode (16) covered with a layer (17) of a dielectric material and coupled capacitively to an upper electrode (18),
    said MOS device (4) is overlaid by at least one metallization layer (10,13), which metallization layer (10,13) is covered with at least one top insulating layer (11,14), that the capacitive element (5) is formed on the top insulating layer (11,14), and that said metallization layer (10,13) extends only between said MOS device (4) and said capacitive element (5).

    摘要翻译： 一种集成在半导体衬底（3）中并由与电容元件（5）串联连接的MOS器件（4）组成的存储单元（2），其中MOS器件（4）具有第一和第二导电端子（6） ，所述电容元件（5）具有被电介质材料的层（17）覆盖并且电容地耦合到上电极（18）的下电极（16），所述MOS器件（4）被至少一个金属化层 （10,13），所述金属化层（10,13）被至少一个顶部绝缘层（11,14）覆盖，所述电容元件（5）形成在顶部绝缘层（11,14）上，以及 所述金属化层（10,13）仅在所述MOS器件（4）和所述电容元件（5）之间延伸。