公开(公告)号：EP3531560A1

公开(公告)日：2019-08-28

申请号：EP19157120.7

申请日：2019-02-14

申请人： STMicroelectronics S.r.l.

发明人： ROSSELLI, Salvatore Marco ,  GUARNACCIA, Giuseppe

IPC分类号： H03M7/16 ,  G06F5/06 ,  G11C7/22

摘要： A Binary-to-Gray conversion circuit (240b is described. The Binary-to-Gray conversion circuit (240b) comprises:
- an input configured to receive a first binary signal (PTR_target),
- a register (61) configured to store a second binary signal (PTRf),
- a prediction circuit (62) configured to receive at input said second binary signal (PTRf) and provide at output a set of binary candidate values (63a-63c), wherein the respective Gray equivalent of each binary candidate value (63a-63c) has a Hamming distance of one from the Gray equivalent of said second binary signal (PTRf),
- an arbiter (66) configured to select one of said binary candidate values (63a-63c) as a function of said first binary signal (PTR_target) and said second binary signal (PTRf), wherein the selected binary candidate value is provided at input to said register (61);
- an encoder block (68) configured to receive the selected binary candidate value and output the Gray encoded equivalent (PTR_gray) of the selected binary candidate value.

公开(公告)号：EP2026493A1

公开(公告)日：2009-02-18

申请号：EP07114463.8

申请日：2007-08-16

申请人： STMicroelectronics S.r.l.

发明人： MANGANO, Daniele ,  GUARNACCIA, Giuseppe ,  PISTRITTO, Carmelo

IPC分类号： H04L7/02 ,  G06F1/12 ,  G06F13/40 ,  G06F5/06

CPC分类号： H04L7/02 ,  H04L7/0008 ,  H04L7/005

摘要： Full-duplex communication over a communication link between an initiator (IN, NI) operating with an initiator clock (IP CLK) and a target (TA, R) operating with a target clock (NoC CLK) involves, in communication from the initiator (IN, NI) to the target (TA, R) the steps of:
- storing data from the initiator (IN, NI) in a first FIFO memory (320) with the initiator clock (IP CLK),
- reading (324) data from the initiator (IN, NI) stored in the first FIFO memory (320), wherein reading is with the target clock (Noc CLK')
- transmitting (12, 18, 24) the data read from the first FIFO memory (320) over a first mesochronous link (19), and
- storing (28) the data transmitted over the first mesochronous link (19) in a buffer (26) whereby said data are made available to the target (TA, R).
Communication from the target (TA, R) to the initiator (IN, NI) includes the steps of:
- transmitting (14, 22, 28) data from the target (TA, R) over a second mesochronous link (29), and
- storing (18, 344) the data transmitted (14, 22, 28) over the second mesochronous link (29) in a second FIFO memory (340), wherein storing is with the target clock (NoC CLK'), whereby the data are made available to said initiator (IN, NI) for reading from the second FIFO memory (340) with the initiator clock signal (IP CLK).

摘要翻译： 通过以起始时钟（IP CLK）操作的发起者（IN，NI）与以目标时钟（NoC CLK）操作的目标（TA，R）之间的通信链路的全双工通信涉及从发起者（ IN，NI）到目标（TA，R）的步骤： - 将来自发起者（IN，NI）的数据存储在具有启动器时钟（IP CLK）的第一FIFO存储器（320）中， - 读取（324）数据 存储在第一FIFO存储器（320）中的发起者（IN，NI），其中读取与从第一FIFO存储器（320）读取的数据的目标时钟（Noc CLK'） - 发送（12,18,24） 通过第一中间同步链路（19），以及 - 将（28）通过第一中间同步链路（19）发送的数据存储在缓冲器（26）中，由此所述数据对目标（TA，R）可用。 从目标（TA，R）到发起者（IN，NI）的通信包括以下步骤： - 通过第二中间同步链路（29）从目标（TA，R）传输（14,22,28）数据，以及 - 在第二FIFO存储器（340）中存储（18,344）在第二中间同步链路（29）上发送的数据（14,22,28），其中存储与目标时钟（NoC CLK'），由此数据 对于所述启动器（IN，NI）可用于利用发起者时钟信号（IP CLK）从第二FIFO存储器（340）读取。