摘要:
A clock generator in apparatus such as e.g. a microcontroller unit is calibrated by aligning at subsequent calibration times the frequency of a first clock (106) with respect to the frequency of a second clock (108) having a higher frequency accuracy than said first clock (106), with the frequency of the first clock (106) which h varies between subsequent calibration times. The frequency of the first clock (106) is aligned to a frequency which is offset by a certain amount with respect to the frequency of the second clock (108) in order counter frequency error which may accumulate over time due to the variation in the frequency of the first clock (106).
摘要:
A method of interfacing a LC sensor (10) with a control unit (20) is described. Specifically, the control unit comprises a first (202) and a second (204) contact, wherein the LC sensor (10) is connected between the first (202) and the second (204) contact, and wherein a capacitor (C1) is connected between the first contact (202) and a ground (GND). In particular, in order to start the oscillation of the LC sensor, the method comprising the steps of: - during a first phase, connecting the first contact (202) to a supply voltage (VDD) and placing the second contact (204) in a high impedance state, such that the capacitor (C1) is charged through the supply voltage (VDD); - during a second phase (2004), placing the first contact (202) in a high impedance state and connecting the second contact (204) to the ground (GND), such that the capacitor (C1) transfers charge towards the LC sensor (10); and - during a third phase (2006), placing the first contact (202) and the second contact (204) in a high impedance state, such that the LC sensor (10) is able to oscillate.
摘要:
A serial protocol interface in a communication device (MD) exchanging data (MOSI, MISO) over a communication link (121, 122, 123) is operated by: - sending output data (MOSI) on (122) the communication link, and - receiving input data (MISO) on (121) the communication link, these input data (MISO) being synchronous with a clock signal (SCK, SCLK) generated at the communication device (MD) and propagated (123) over the communication link (121, 122, 123), - initializing operation by exchanging data over the communication link (121, 122, 123) by sending output data (MOSI) on the communication link (122) at a first data rate, - detecting a signal transition in the input data (MISO) received on the communication link (121), and - once such a transition is detected, exchanging data over the communication link (121, 122, 123) at a second data rate, higher than the first data, with the exchanging of data at a second data rate synchronized (18) as a function of said signal transition.
摘要:
A method of interfacing a LC sensor (10) with a control unit (280) is described. Specifically, the control unit (280) comprises a first (202) and a second (204) contact, and the LC sensor (10) is connected between the first (202) and the second (204) contact. In particular, the method comprising: - starting the oscillation of the LC sensor (10); - monitoring the voltage (V 204 ) at the second contact (204), wherein the voltage (V 204 ) at the second contact (204) corresponds to the sum of the voltage (V MID ) at the first contact (202) and the voltage at the LC sensor (10); and - varying the voltage (V MID ) at the first contact (202) such that the voltage (V 204 ) at the second contact (204) does not exceed an upper voltage threshold and does not fall below a lower voltage threshold.
摘要:
In an embodiment, a method of managing memories (10) includes: - providing a first (11) memory module and a second memory module (12) each including a first (R1, R2) and a second (R4, R3) partition, - writing first data (DATA1) in the first partition (R1) of the first memory module (11) and second data (DATA2) in the first partition (R2) of the second memory module (12), and - selectively operating the first (11) and second (12) memory modules in a first operating mode or a second operating mode, where: - in the first operating mode, parity bits (PAR1) for the first data (DATA1) are written in the second partition (R3) of the second memory module (12) and parity bits (PAR2) for the second data (DATA2) are written in the second partition (R4) of the first memory module (11), - in the second operating mode, further data (ED1, ED2) are written in the place of parity bits (PAR1, PAR2) in the second partition (R4, R3) of one or both the first memory module (11) and the second memory module (12).
摘要:
A system for interfacing an LC sensor (10) is described. The system comprises means (206) configured to selectively start an oscillation of the LC sensor (10). The system comprises also an analog peak detector (280) configured to determine a signal ( V peak ) being indicative of a peak voltage of the oscillation of the LC sensor (10) and detection means (208, 230) configured to determine the state of the LC sensor (10) as a function of the signal ( V peak ) determined by the analog peak detector (280).
摘要:
La présente description concerne un dispositif (60) comprenant : un circuit électronique (20) ; un circuit oscillant (12) comprenant un quartz (14), configuré pour fournir un signal d'horloge au circuit électronique (20) ; et un élément chauffant (62) configuré pour augmenter la température du quartz (14).
摘要:
A serial protocol interface in a communication device (MD) exchanging data (MOSI, MISO) over a communication link (121, 122, 123) is operated by: - sending output data (MOSI) on (122) the communication link, and - receiving input data (MISO) on (121) the communication link, these input data (MISO) being synchronous with a clock signal (SCK, SCLK) generated at the communication device (MD) and propagated (123) over the communication link (121, 122, 123), - initializing operation by exchanging data over the communication link (121, 122, 123) by sending output data (MOSI) on the communication link (122) at a first data rate, - detecting a signal transition in the input data (MISO) received on the communication link (121), and - once such a transition is detected, exchanging data over the communication link (121, 122, 123) at a second data rate, higher than the first data, with the exchanging of data at a second data rate synchronized (18) as a function of said signal transition.