公开(公告)号：EP1667158A1

公开(公告)日：2006-06-07

申请号：EP04105354.7

申请日：2004-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： PISASALE, Michelangelo ,  GAIBOTTI, Maurizio ,  LA PLACA, Michele

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C5/147 ,  G11C16/30

Abstract: A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

Abstract translation: 提出了用于提供低于转换器的电源电压（Vdd）的输出电压（Vo）的降压转换器（125）。 转换器包括电压调节装置（205），用于通过利用控制信号（Vg）控制可变电导率元件（Tr）来获得与来自电源电压的输出电压相对应的中间电压（Vr） 用于通过控制另外的可变电导率元件（Tsb，T 1 -TN）来获得来自电源电压的输出电压的输出级（220,225×1〜225N）的中间电压（Vr）和参考电压（Vbg） 与所述控制信号相关联，其中所述另一可变导电元件具有至少一个多个基本模块（225 1至225 N）的组（MM，ML，MH）的模块化结构，所述转换器还包括装置（230，SW 1 - SW N），用于根据输出电压和中间电压之间的比较来连续地启用和/或禁用每组的模块。

公开(公告)号：EP3859738A1

公开(公告)日：2021-08-04

申请号：EP21153082.9

申请日：2021-01-22

Applicant: STMicroelectronics S.r.l.

Inventor： PERRONI, Maurizio Francesco ,  DISEGNI, Fabio Enrico Carlo ,  LA PLACA, Michele ,  TORTI, Cesare

IPC: G11C13/00 ,  G11C5/14 ,  G11C7/14

Abstract: A voltage generation circuit (30), for a non-volatile memory device (20) having a memory array (21) with a plurality of memory cells (2) coupled to respective wordlines (WL) and local bit-lines (BL), each of which has a storage element (2a) and a selector element (2b), a bipolar transistor being coupled to the storage element (2a) so as to enable selective flow of a cell current (I cell ) during reading or verifying operations, and a base terminal of the selector element being coupled to a respective wordline; associated to each bitline is a biasing transistor (7) having a control terminal, and the voltage generation circuit (30) generates a cascode voltage (V casc ) for this control terminal; a driver stage (15) is coupled to one end of each wordline. The voltage generation circuit generates the cascode voltage (V casc ) based on a reference voltage (V ref ), which is a function of the emulation of a voltage drop on the driver stage, on the wordline, and on the memory cell as a result of a current associated to the corresponding selector element.

公开(公告)号：EP1667158B1

公开(公告)日：2007-01-31

申请号：EP04105354.7

申请日：2004-10-28

Applicant: STMicroelectronics S.r.l.

Inventor： PISASALE, Michelangelo ,  GAIBOTTI, Maurizio ,  LA PLACA, Michele

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C5/147 ,  G11C16/30