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1.发明公开
公开(公告)号：EP3817001A1
公开(公告)日：2021-05-05
申请号：EP20202266.1
申请日：2020-10-16
Applicant: STMicroelectronics S.r.l.
IPC: G11C13/00
Abstract: The present invention relates to a method for programming a phase-change memory device (1) of differential type. The method comprises the following operations. In a first time interval (T1), programming a direct memory cell or the respective complementary one associated with a first programming driver (PGL[0]) by means of a current between SET and RESET; in the same first time interval (T1), simultaneously programming a direct memory cell or the respective complementary one associated with a second programming driver (PGL[1]) by means of the same current between SET and RESET. In a second time interval (T2), programming the other direct memory cell or the respective complementary one associated with the first programming driver (PGL[0]) by means of the other current between SET and RESET; in the same second time interval (T2), simultaneously programming the other direct memory cell or the respective complementary one associated with the second programming driver (PGL[1]) by means of the same other current between SET and RESET.
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公开(公告)号：EP3364415A1
公开(公告)日：2018-08-22
申请号：EP18157965.7
申请日：2018-02-21
Applicant: STMicroelectronics S.r.l.
Inventor： MANFRE', Davide , TORTI, Cesare , DISEGNI, Fabio Enrico Carlo
Abstract: A phase-change memory device has a low-voltage connection path (3), configured to connect, in an operational phase of the device (1), an access terminal (5) to a selected bit line (8) of the plurality of bit lines; and a high-voltage connection path (4), configured to connect, in the operational phase of the device (1), the access terminal (5) to the selected bit line (8), in parallel with the low-voltage connection path (3).
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3.发明公开
公开(公告)号：EP3822973A1
公开(公告)日：2021-05-19
申请号：EP20207619.6
申请日：2020-11-13
Applicant: STMicroelectronics S.r.l.
Inventor： DISEGNI, Fabio Enrico Carlo , PERRONI, Maurizio Francesco , TORTI, Cesare , SCARDINO, Giuseppe
Abstract: A non-volatile memory device (100) including an array (102A_R) of memory cells (3) coupled to word lines (WL_dx) and a row decoder (105), which includes a first and a second pull-down stage (115L, 115R), which are arranged on opposite sides of the array (102A_R), and include, respectively, for each word line (WL_dx), a corresponding first pull-down switching circuit (112L) and a corresponding second pull-down switching circuit (112R), which are coupled to a first point (E sx ) and a second point (E dx ), respectively, of the first word line (WL_dx). The row decoder (105) moreover comprises a pull-up stage (118), which includes, for each word line (WL_dx), a corresponding pull-up switching circuit (122R, 126R, 199), which can be electronically controlled in order to: couple the first point (E sx ) to a supply node (V DD ) in the step of deselection of the word line (WL_dx); and decouple the first point (E sx ) from the supply node (V DD ) in the step of selection of the word line (WL_dx).
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公开(公告)号：EP3382566A1
公开(公告)日：2018-10-03
申请号：EP18163468.4
申请日：2018-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： DISEGNI, Fabio Enrico Carlo , GOLLER, Federico , FEBBRARINO, Michele
IPC: G06F13/16
Abstract: Module for managing operations for accessing a Flash memory (3) on the basis of requests received from a main CPU (12) and from an auxiliary CPU (14), configured for: associating, with the main CPU, a higher access priority to the Flash memory (3) than the access priority of the auxiliary CPU (14); commanding (104; 108), in the absence of further requests for accessing the Flash memory (3), the access to the Flash memory (3) for the main or auxiliary CPU which has initiated a first access request; verifying (104; 108), following a receipt of a second access request, the access priority associated with this second access request; suspending (106; 110) one of the first or the second access request having lower priority; and authorizing (104; 108) the other of the first or the second access request having higher priority.
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公开(公告)号：EP4227943A1
公开(公告)日：2023-08-16
申请号：EP23151295.5
申请日：2023-01-12
Applicant: STMicroelectronics S.r.l.
Inventor： DISEGNI, Fabio Enrico Carlo , GOLLER, Federico , FALANGA, Dario , FEBBRARINO, Michele , MONTANARO, Massimo
IPC: G11C7/22
Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.
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Patent Agency Ranking
公开(公告)号：EP4191647A1
公开(公告)日：2023-06-07
申请号：EP22207185.4
申请日：2022-11-14
Inventor： GIACOMINI, Mauro , DISEGNI, Fabio Enrico Carlo , NARWAL, Rajesh , SAINI, Pravesh Kumar , HARESHBHAI NIRANJANI, Mayankkumar
Abstract: An assembly for detecting a structural defect in a semiconductor die (30), comprising a defect-detection sensor and computing means (43), wherein the defect-detection sensor includes: a plurality of resistive paths (38a-d) of electrical-conductive material in the semiconductor die (30), each of which has a first end (39') and a second end (39") and extends proximate a perimeter (32a) of the semiconductor die; and a plurality of signal-generation structures (40a-40d, 45), each coupled to a respective resistive path (38a-d) and configured to supply a test signal to the resistive path (38a-d). The computing means are configured to: control the signal-generation structures to generate the test signals; acquire the test signals in each resistive paths (38a-d); test an electrical feature of the resistive paths (38a-d) by performing an analysis of the test signals acquired; and detect the presence of the structural defect in the semiconductor die (30) based on a result of the analysis of the test signals acquired.
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公开(公告)号：EP3913630A1
公开(公告)日：2021-11-24
申请号：EP21175272.0
申请日：2021-05-21
Inventor： DISEGNI, Fabio Enrico Carlo , CAPECCHI, Laura , CARISSIMI, Marcella , RANA, Vikas , TORTI, Cesare
Abstract: A non-volatile memory device including: an array (2) of memory cells (3) arranged in rows and columns; a plurality of local bitlines (BL), the memory cells (3) of each column being coupled to a corresponding local bitline (BL); a plurality of main bitlines (MBL), each main bitline (MBL) being coupleable to a corresponding subset of local bitlines (BL); a plurality of program driver circuits (19' ; 19" ; 19'''), each of which has a corresponding output node (N out ) and injects a programming current (I*) in the corresponding output node (N out ), each output node (N out ) being coupleable to a corresponding subset of main bitlines (MBL;MBL -MBL ). Each program driver circuit (19' ; 19" ; 19"') further includes a corresponding limiter circuit (35) which is electrically coupled, for each main bitline (MBL;MBL -MRL ) of the corresponding subset, to a corresponding sense node (N out ; MBL -MBL ) whose voltage depends, during a step of writing, on the voltage on the corresponding bitline (MBL;MBL -MBL ). Each limiter circuit (35) turns off the corresponding programming current (T*), in case the voltage (V out ; V MBL ) on any of the corresponding sense nodes (N out ; MBL -MBL ) overcomes a reference voltage (V clamp +V th40 ;V clamp +V th40' ).
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公开(公告)号：EP3382566B1
公开(公告)日：2020-03-04
申请号：EP18163468.4
申请日：2018-03-22
Applicant: STMicroelectronics S.r.l.
Inventor： DISEGNI, Fabio Enrico Carlo , GOLLER, Federico , FEBBRARINO, Michele
IPC: G06F13/16
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9.发明公开CIRCUIT AND METHOD FOR BIASING NON-VOLATILE MEMORY CELLS 有权SCHALTUNG UND VERFAHREN ZUM VORSPANNENNICHTFLÜCHTIGERSPEICHERZELLEN
公开(公告)号：EP3136395A1
公开(公告)日：2017-03-01
申请号：EP16162017.4
申请日：2016-03-23
Applicant: STMicroelectronics S.r.l.
Abstract: A circuit for biasing non-volatile memory cells includes: a dummy decoding path (18) between a global bias line (33) and a biasing node (25; 125); a reference current generator (15), coupled to the dummy decoding path (18) and configured to supply a reference current (I T ); a biasing stage (16, 17) configured to set a cell bias voltage (V BDC ) on the biasing node (25); and a compensation stage (20), configured to compensate a current absorption of the biasing stage (16, 17) at the biasing node (25) so that the reference current (I T ) will flow through the dummy decoding path (18).
Abstract translation: 用于偏置非易失性存储单元的电路包括：全局偏置线（33）和偏置节点（25; 125）之间的虚拟解码路径（18）。 参考电流发生器（15），耦合到所述虚拟解码路径（18）并且被配置为提供参考电流（I T）; 偏置级（16,17），被配置为在所述偏置节点（25）上设置单元偏置电压（V BDC）; 以及补偿级（20），被配置为补偿偏置节点（25）处的偏置级（16,17）的电流吸收，使得参考电流（I T）将流过虚拟解码路径（18）。
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10.发明公开
公开(公告)号：EP4210056A1
公开(公告)日：2023-07-12
申请号：EP22208619.1
申请日：2022-11-21
Applicant: STMicroelectronics S.r.l.
Inventor： TOMASONI, Alessandro , DISEGNI, Fabio Enrico Carlo , CARISSIMI, Marcella , LO IACONO, Daniele
Abstract: A method for storing information in a coded manner in non-volatile memory cells, providing a group of non-volatile memory cells (11A, 11B, 11C, 11D) of non volatile memory, the memory cell being of the type in which a stored logic state (A, B, C, D), which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current (IcellA, IcellB, IcellC, IcellD) provided by the cell (11A, 11B, 11C, 11D), comprising a determined number (Nc) of non-volatile memory cells which is greater than two, the group of non-volatile memory cells (11A, 11B, 11C, 11D) storing a codeword (CW) formed by the values of said stored states (A, B, C, D) of the cells (11A, 11B, 11C, 11D) of the group taken according to a given order,
wherein
given a set of codewords (CW) obtainable by the stored values (A, B, C, D) in the determined number of non-volatile memory cells (11A, 11B, 11C, 11D) in a group,
storing the information in at least two subsets (SB1, SB2, SB3; SB'1, SB'2) of said set of codewords (CW) comprising each at least a codeword (CW), each codeword (CW) in a same subset having a same Hamming weight,
each codeword (CW) belonging to one subset (SB1, SB2, SB3; SB'1, SB'2) having a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.
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