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1.发明公开MOS device and process for manufacturing MOS devices using dual-polysilicon layer technology 有权MOS器件和制造MOS器件具有两层多晶硅技术的方法
公开(公告)号：EP1434257A3
公开(公告)日：2004-12-15
申请号：EP03104939.8
申请日：2003-12-23
IPC分类号： H01L27/115 , H01L21/8247 , H01L29/423
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11524 , H01L27/11534
摘要： An MOS device has a stack (40) and a passivation layer (45) covering the stack. The stack (40) is formed by a first polysilicon region (34) and by a second polysili con region (36) arranged on top of one another and separated by an intermediate dielectric region (35). An electrical connection region (53a), formed by a column structure substantially free of steps, extends through the passivation layer (45), the second polysilicon region (36) and the intermediate dielectric region (35), and terminates in contact with the first polysilicon region (34) so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electr ical connection region (53a) requires just one mask.
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2.发明公开MOS device and process for manufacturing MOS devices using dual-polysolicon layer technology 有权Verfahren zur Herstellung von MOS Bauelementen mit Zweischicht Polysilizium Technik
公开(公告)号：EP1434257A2
公开(公告)日：2004-06-30
申请号：EP03104939.8
申请日：2003-12-23
IPC分类号： H01L21/00
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11524 , H01L27/11534
摘要： An MOS device has a stack (40) and a passivation layer (45) covering the stack. The stack (40) is formed by a first polysilicon region (34) and by a second polysili con region (36) arranged on top of one another and separated by an intermediate dielectric region (35). An electrical connection region (53a), formed by a column structure substantially free of steps, extends through the passivation layer (45), the second polysilicon region (36) and the intermediate dielectric region (35), and terminates in contact with the first polysilicon region (34) so as to electrically contacting the first polysilicon region and the second polysilicon region. Fabrication of the electr ical connection region (53a) requires just one mask.
摘要翻译： MOS器件具有覆盖堆叠的堆叠（40）和钝化层（45）。 堆叠（40）由第一多晶硅区域（34）和由彼此顶部布置并由中间介电区域（35）隔开的第二聚合区域（36）形成。 由基本上没有台阶的柱结构形成的电连接区域（53a）延伸穿过钝化层（45），第二多晶硅区域（36）和中间介质区域（35），并终止于第一 多晶硅区域（34），以便与第一多晶硅区域和第二多晶硅区域电接触。 电连接区域（53a）的制造仅需要一个掩模。
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3.发明公开MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact 有权MOS器件以及使用具有侧触点的双多晶硅层技术制造MOS器件的工艺
公开(公告)号：EP1434258A3
公开(公告)日：2004-12-15
申请号：EP03104938.0
申请日：2003-12-23
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A MOS device has: a semiconductor body (30) defining a surface (30a); a stack (40) on top of the semiconductor body; and a passivation layer (45) on top of the semiconductor body and covering the stack. The stack (40) is formed by a first polysilicon region (34) and by a second polysilicon region (36) arranged on top of it and separated by an intermediate dielectric region (35). An electrical connection region (24) extends through the passivation layer (45) to the surface (30a) of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.
摘要翻译： MOS器件具有：限定表面（30a）的半导体主体（30） 在半导体主体的顶部上的堆叠（40） 以及在半导体本体的顶部上并且覆盖堆叠的钝化层（45）。 堆叠（40）由第一多晶硅区域（34）和第二多晶硅区域（36）形成，第二多晶硅区域（36）布置在其顶部并且被中间电介质区域（35）分开。 电连接区域（24）相对于第一和第二多晶硅区域横向地延伸穿过钝化层（45）到达半导体本体的表面（30a），并与第一和第二多晶硅区域电接触。
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4.发明公开MOS device and a process for manufacturing MOS devices using a dual-polysilicon layer technology with side contact 有权MOS ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten ten
公开(公告)号：EP1434258A2
公开(公告)日：2004-06-30
申请号：EP03104938.0
申请日：2003-12-23
IPC分类号： H01L21/285
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/511
摘要： A MOS device has: a semiconductor body (30) defining a surface (30a); a stack (40) on top of the semiconductor body; and a passivation layer (45) on top of the semiconductor body and covering the stack. The stack (40) is formed by a first polysilicon region (34) and by a second polysilicon region (36) arranged on top of it and separated by an intermediate dielectric region (35). An electrical connection region (24) extends through the passivation layer (45) to the surface (30a) of the semiconductor body laterally with respect to, and in contact with, the first and the second polysilicon regions so as to contact them electrically.
摘要翻译： MOS器件具有：限定表面（30a）的半导体本体（30）; 在所述半导体主体的顶部上的叠层（40）; 以及钝化层（45），其位于半导体主体的顶部并覆盖该堆叠。 堆叠（40）由第一多晶硅区域（34）和布置在其顶部并由中间介质区域（35）分隔的第二多晶硅区域（36）形成。 电连接区域（24）相对于第一和第二多晶硅区域相对于第一和第二多晶硅区域横向地延伸穿过钝化层（45）到半导体本体的表面（30a），以便与它们电接触。
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