摘要:
In a current mode, PWM integrated drive system of an external load (VCM) a switched-capacitor amplifier with a Sample & Hold stage connected in cascade thereto as the current sensing amplifier of the control loop, overcomes the criticality of inevitable resistive mismatchings, thus permitting a scaling down of the integrated drive system while preserving a high precision.
摘要:
The monitoring the current lowing through an inductive load driven through a bridge power stage in a PWM mode, by using a pair of complementary periodic reference signals and amplifying by a sensing amplifier the signal existing on of a current sensing resistor functionally connected in series with the load, for producing an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of said bridge stage, comprises sampling the signal output by the sensing amplifier with a Sample & Hold circuit comprising a sampling switch and a storing capacitor. The average value of the current in the load in monitored by sampling at an instant half way an active driving phase and at an instant half way a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half instant of said phases of operation. The synchronizing pulse is generated in coincidence with the peak and with the virtual zero crossing of said two reference periodic signals, outphased by 180 degrees. A two-input logic AND gate, combining said synchronizing pulse and a masking signal of a preestablished duration generated at every switching of said bridge stage may also be employed.
摘要:
The sensing of the rotor position for synchronizing the drive of a multiphase brushless motor when driven in a "multipolar" mode is carried out by interrupting the driving current in at least one of the windings of the motor coupled with a zero-cross sensing circuit of the BEMF signal (BEMF DETECT CIRCUIT), by means of a first logic signal (ENABLE), enabling a logic gate (AND) for asserting a zero-cross event detected by the circuit, by a second logic signal (MASK) and simultaneously resetting the first (ENABLE) and second (MASK) signals after a certain period of time from the instant of interruption.