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10 条记录 (耗时 0.01 秒)

    High voltage level shifter for driving an output stage
    5.
    发明公开
    High voltage level shifter for driving an output stage 失效
    用于驱动输出级的高电平电平转换器

    公开(公告)号：EP0913927A1

    公开(公告)日：1999-05-06

    申请号：EP97830561.3

    申请日：1997-10-31

    申请人： STMicroelectronics S.r.l.

    发明人： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

    IPC分类号： H03F1/00 ,  H03K19/0185

    CPC分类号： H03K19/018585

    摘要： The invention relates to an electronic level shifter circuit (1) for driving a high-voltage output stage (2). This output stage (2) comprises a complementary pair (3) of transistors (I36,I32) connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (I32) connected in series with an NMOS pull-down transistor (I36). An additional transistor (I34) is connected in parallel with the pull-up transistor (I32), and the driver circuit (1) has a first output (A) connected to the control terminal of the pull-up transistor (I32) and a second output connected to the control terminal of the additional transistor (I34).

    摘要翻译： 本发明涉及用于驱动高压输出级（2）的电子电平移位器电路（1）。 该输出级（2）包括连接在第一（Vdd）和第二（Vss）电源电压基准之间的晶体管（I36，I32）的互补对（3）和至少一个串联连接的PMOS上拉晶体管（I32） 用NMOS下拉晶体管（I36）。 附加晶体管（I34）与上拉晶体管（I32）并联连接，并且驱动器电路（1）具有连接到上拉晶体管（I32）的控制端子的第一输出（A）和 第二输出端连接到附加晶体管（I34）的控制端。

    High voltage output stage for driving an electric load
    9.
    发明公开
    High voltage output stage for driving an electric load 失效
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    公开(公告)号：EP0913925A1

    公开(公告)日：1999-05-06

    申请号：EP97830559.7

    申请日：1997-10-31

    申请人： STMicroelectronics S.r.l.

    发明人： Depetro, Riccardo ,  Martignoni, Fabrizio ,  Scian, Enrico

    IPC分类号： H03F1/00 ,  H03K19/0185

    CPC分类号： H03K19/018585

    摘要： The invention relates to a high-voltage final output stage (1) for driving an electric load, of the type which comprises a complementary pair (3) of transistors connected between first (Vdd) and second (Vss) supply voltage references, and at least one PMOS pull-up transistor (MP1) connected in series with an NMOS pull-down transistor (MN). The stage (1) comprises an additional PMOS transistor (MP2) connected in parallel with the pull-up transistor (MP1) and having the body terminal in common therewith. More particularly, the body terminals of both PMOS transistors (MP1,MP2) are formed in the semiconductor within a common well which can withstand high voltages, and the additional transistor (MP2) is a thick oxide PMOS power transistor.

    摘要翻译： 本发明涉及用于驱动电负载的高压最终输出级（1），其包括连接在第一（Vdd）和第二（Vss）电源电压基准之间的晶体管的互补对（3），并且在 与NMOS下拉晶体管（MN）串联连接的至少一个PMOS上拉晶体管（MP1）。 级（1）包括与上拉晶体管（MP1）并联连接并且与其主体端子共同连接的附加PMOS晶体管（MP2）。 更具体地说，两个PMOS晶体管（MP1，MP2）的主体端子形成在可承受高电压的公共阱内的半导体中，附加晶体管（MP2）是厚氧化物PMOS功率晶体管。

    Method and corresponding circuit to prevent a parasitic transistor turn on in an output stage of an electronic circuit
    10.
    发明公开
    Method and corresponding circuit to prevent a parasitic transistor turn on in an output stage of an electronic circuit 失效
    用于防止导通寄生晶体管的电子电路的输出级的方法和相应的电路

    公开(公告)号：EP0889591A1

    公开(公告)日：1999-01-07

    申请号：EP97830327.9

    申请日：1997-06-30

    申请人： STMicroelectronics S.r.l.

    发明人： Scian, Enrico ,  Martignoni, Fabrizio ,  Depetro, Riccardo

    IPC分类号： H03K17/10 ,  H03K19/003 ,  G05F3/20 ,  H01L27/02

    CPC分类号： H03K19/00315 ,  G05F3/205 ,  H01L27/0251

    摘要： The invention relates to a method, and related circuit, for preventing the triggering of a parasitic transistor in an output stage (2) of an electronic circuit, said stage (2) comprising a transistor pair (M1,M2) with at least one transistor (M2) of the pull-up PMOS type having respective source, gate and drain terminals and a body terminal, and a parasitic bipolar transistor (3) having a terminal connected to said body terminal, characterized in that it comprises the steps of:

    providing a capacitor (C1) connected between the body and source terminals of the PMOS transistor;
    using a control circuit (5) to suppress the body effect of the pull-up PMOS transistor.

    摘要翻译： 本发明涉及一种方法，以及相关的电路，用于在一个电子电路的输出级（2）防止寄生晶体管的触发，所述步骤（2）包括一个晶体管对（M1，M2），具有至少一个晶体管 上拉PMOS的（M2）型具有respectivement源极，栅极和漏极端子和主体端子，和（3），其具有连接到所述主体端子的端子，在做了它包括以下步骤为特征的寄生双极晶体管：提供 连接在PMOS晶体管的体端子与源极端之间的电容器（C1）; 使用控制电路（5），以抑制PMOS上拉晶体管的体效应。