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    NAND flash memory with erase verify based on shorter delay before sensing
    3.
    发明公开
    NAND flash memory with erase verify based on shorter delay before sensing 有权
    NAND闪存擦除验证基于传感之前更短的延迟

    公开(公告)号：EP1752989A1

    公开(公告)日：2007-02-14

    申请号：EP05106976.3

    申请日：2005-07-28

    申请人： STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    发明人： Bovino, Angelo ,  Micheloni, Rino ,  Ravasio, Roberto

    IPC分类号： G11C16/32 ,  G11C16/26 ,  G11C16/34

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/344

    摘要： A non-volatile memory device (100) is proposed. The non-volatile memory device includes a plurality of memory cells (110) each one having a programmable threshold voltage, and means for reading (130, 140, 150) a set of selected memory cells with respect to a plurality of reference voltages, for each selected memory cell the means for reading including means for charging (Pc) a reading node (BL) associated with the selected memory cell with a charging voltage (Vc), means for biasing (130) the selected memory cell with a biasing voltage, means for connecting (120d, 120s) the charged reading node with the biased selected memory cell, and means for sensing (205) a voltage at the reading node after a predefined delay from the connection, for at least a first one of the reference voltages (V R ) the biasing voltage being a first biasing voltage equal to the first reference voltage and the delay being a common first delay (Te), wherein for at least a second one of the reference voltages (Vga) the biasing voltage is a second biasing voltage (V R ) different from the second reference voltage, and the delay is a second delay (Teg) different from the first delay.

    摘要翻译： 一种非易失性存储器设备（100）提议。 非易失性存储器设备包括存储器单元的多个（110）每一个具有可编程阈值电压的装置，以及用于读出（130，140，150）相对于一组选定的存储器单元内的基准电压复数，用于 每个所选择的存储单元中的装置，用于读取包括用于充电（PC）读出节点（BL）用的充电电压所选择的存储器单元相关联（VC），用于偏置（130）所述选定存储器单元与偏置电压， 装置，用于连接（120D，120秒）与该偏置的选定存储器单元中的电荷的读出节点的装置，以及用于感测（205）在从所述连接的预定义的延迟之后读出节点的电压，对于参考电压中的至少一个第一个 （VR）的偏置电压是一个第一偏置电压等于所述第一基准电压和所述延迟是共同的第一延迟（TE），worin对于参考电压中的至少一个第二个（VGA）的偏置电压是一个第二偏置 电压 （V R）从所述第二参考电压不同，并且延迟为第二延迟（TEG）与所述第一延迟不同。

    Configuration of a multi-level flash memory device
    5.
    发明公开
    Configuration of a multi-level flash memory device 有权
    Konfigurierung eines Multibit-Flashspeichers

    公开(公告)号：EP1750277A1

    公开(公告)日：2007-02-07

    申请号：EP05425559.1

    申请日：2005-07-28

    申请人： STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    发明人： Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC分类号： G11C11/56 ,  G11C16/20

    CPC分类号： G11C11/5621 ,  G11C16/20

    摘要： A multilevel flash memory device of enhanced performance allows for a faster and more effective configuration of the operating parameters of the memory device, for performing the different functioning algorithms of the memory in the most efficient manner as possible.
    The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into "algorithm-friendly" data that are stored in a purposely embedded ancillary random access memory at every power-on of the memory device by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
    The ancillary random access memory capable of storing processed configuration data permits a further simplification and quickening of the trimming operations of the device that are performed during the testing phase of the single device being fabricated, by supporting a enhanced emulation of the many possible configurations and selectable test parameters for identifying optimal configuration and corresponding operating parameters of the memory device, before eventually conditioning (e.g. burning) the corresponding configuration fuses of the fabricated memory device.

    摘要翻译： 具有增强性能的多级闪存器件允许更快更有效地配置存储器件的操作参数，以尽可能以最有效的方式执行存储器的不同功能算法。 通过允许将配置位一次性处理成“算法友好”数据来简化在测试期间存储器件的操作参数的最佳配置，每个功率存储在有意嵌入的辅助随机存取存储器中 - 通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来存储存储器件。 能够存储经处理的配置数据的辅助随机存取存储器允许进一步简化和加快在制造的单个设备的测试阶段期间执行的设备的修整操作，通过支持许多可能配置的增强仿真并且可选择 在最终调节（例如燃烧）所制造的存储器件的相应配置保险丝之前，用于识别存储器件的最佳配置和相应操作参数的测试参数。

    Page buffer for multi-level NAND programmable memories
    8.
    发明公开
    Page buffer for multi-level NAND programmable memories 有权
    Multipegel-NAND-Speicher的程序设计师Seitenspeicher

    公开(公告)号：EP1748445A1

    公开(公告)日：2007-01-31

    申请号：EP05106972.2

    申请日：2005-07-28

    申请人： STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    发明人： Crippa, Luca ,  Missiroli, Chiara ,  Bovino, Angelo ,  Ravasio, Roberto ,  Micheloni, Rino

    IPC分类号： G11C11/56

    CPC分类号： G11C11/5628

    摘要： A page buffer (130) for an electrically programmable memory (100) is provided. The electrically programmable memory includes a plurality of memory cells (110) arranged in a plurality of bit lines (BLe,BLo) of memory cells and forming a plurality of individually-selectable memory sets. The electrically programmable memory includes a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell. The data bits include at least a first data bits group (MSB) and a second data bits group (LSB), the first data bits groups and, respectively, the second data bits groups stored in the memory cells of one of said individually-selectable memory cell sets forming at least a first memory page and a second memory page, respectively. The first and second memory pages are individually addressable in reading and writing. The page buffer comprises at least one read/program unit (205) having a coupling line (SO) operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cells sets. The read/program unit comprises enabling means (230-1, 230-2, 252, 254, 256, 258, 272, 274, 276, 278) for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits (MSB) of the selected memory cell, and an existing data value already stored in the second group of data bits (LSB) of the selected memory cell. The enabling means comprise reading means (256, 258, 260, 230-2) for retrieving the existing data value; means (252, 254, 230-1) for receiving an indication of the target data value; combining means (272, 274, 276, 278) for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication; and conditioning means (272, 274) included in the combining means for conditioning a potential of the coupling line based on the existing data value and the modified indication, so as to cause the coupling line to take the program enabling potential or the program inhibition potential.

    摘要翻译： 提供了一种用于电可编程存储器（100）的页缓冲器（130）。 电可编程存储器包括布置在存储器单元的多个位线（BLe，BLo）中的多个存储单元（110），并形成多个单独选择的存储器组。 电可编程存储器包括针对每个存储器单元定义的多个不同的编程状态，对应于每个存储单元中可存储的数据位数N> = 2。 数据位包括至少第一数据位组（MSB）和第二数据位组（LSB），第一数据位组和分别存储在所述可单独选择的一个存储单元中的第二数据位组 存储单元组分别形成至少第一存储器页面和第二存储器页面。 第一和第二个存储器页面在读取和写入时可单独寻址。 页面缓冲器包括至少一个具有可操作地与至少一个所述位线相关联的耦合线（SO）的读/写单元（205），并且适于至少临时存储从或写入 存储在所选存储单元组的存储单元中的第一或第二存储器页。 读/程序单元包括启用装置（230-1,230-2,252,254,256,258,272,274,276,278,278,276,278,272,276,278,276,278,278,276,278,276,278,278,276,278,278,276,278,278,276,278,278,276,278,278,278,276,278,278,278,276,278,278,2 行程序中的一个，使程序启用电位和程序禁止电位，调节为要存储在所选择的存储器单元的第一组数据位（MSB）中的目标数据值，以及已经存储在第二个存储单元中的现有数据值 所选存储单元的数据位组（LSB）组。 启用装置包括用于检索现有数据值的读取装置（256,258,260,230-2）; 用于接收目标数据值的指示的装置（252,254,230-1）; 用于将接收到的目标数据值与所检索的现有数据值组合的组合装置（272,274,276,278），从而修改目标数据值的所述指示以获得修改的指示; 以及包括在组合装置中的调节装置（272,274），用于基于现有数据值和修改的指示调节耦合线的电位，以使耦合线采取程序使能电位或编程抑制电位 。

    Method for accessing a multilevel nonvolatile memory device of the flash NAND type
    9.
    发明公开
    Method for accessing a multilevel nonvolatile memory device of the flash NAND type 有权
    Verfahren zum Zugreifen auf einenichtflüchtigeMehrpegelspeichervorrichtung vom Typ FLASH NAND

    公开(公告)号：EP1746604A1

    公开(公告)日：2007-01-24

    申请号：EP05106783.3

    申请日：2005-07-22

    申请人： STMicroelectronics S.r.l. ,  Hynix Semiconductor Inc.

    发明人： Bovino, Angelo ,  Altieri, Vincenzo ,  Ravasio, Roberto ,  Micheloni, Rino ,  De Matteis, Mario

    IPC分类号： G11C11/56

    CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C2211/5641

    摘要： Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

    摘要翻译： 多级编程（30-42）允许通过从第二位（MSB）单独编程（30-32）第一位（LSB）来在所选单元（3）中写入第一位和第二位。 第一位的编程（30-32）确定从第一阈值电平（A）到第二阈值电平（B）的移位（32）; 第二位的编程（36-42）需要初步读取（36-40）来检测第一位（LSB）是否已被修改; 执行第一写入步骤（42），如果第一位已被修改并使单元进入第三阈值电压（C），并执行第二写入步骤（42）以使所选择的单元达到不同的第四阈值电压（D） 如果第一位未被修改，则从第三阈值水平。 存储器阵列（2）被划分为第一部分（2a），其中使用与多个位相对应的多个阈值级别存储数据;以及第二部分（2b），其中使用与单个位对应的两个阈值电平存储数据。 为了增加读取和编程可靠性，在第二部分（2b）的初步读取（40）期间，读取结果被迫对应于第一阈值水平。